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HSP45106 Datasheet(PDF) 8 Page - Intersil Corporation |
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HSP45106 Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 13 page  8 FIGURE 5. SINE/COSINE SECTION BLOCK DIAGRAM FIGURE 6. SERIAL OUTPUT I/O TIMING DIAGRAM FIGURE 7. FREQUENCY TO OUTPUT DELAY OES COS (15:0) FORMAT CONTROL ADDRESS DECODE 16 COSINE 16 SINE OEC DACSTRB OUTPUT CONTROL / 16 / 16 SINE/COSINE ROM SIN/COS ARGUMENT BINFMT R.ENPHAC, TEST, PAR/SER SIN (15:0) / / / 28 / 20 01 2 3 45 6 CLK 7 8 9 10 SERIAL DATA OUTPUT BIT DACSTRB ENPHAC 3 012 tDSO tECS CLK WR A(2:0) C(15:0) ENCFREG ENOFREG COS(15:0), SIN(15:0) WRITE MS INPUT REGISTER WRITE LS INPUT REGISTER TRANSFER DATA TO CENTER OR OFFSET FREQUENCY REGISTER NEW FREQUENCY DATA CS HSP45106 |
Similar Part No. - HSP45106 |
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Similar Description - HSP45106 |
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