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CP82C59A-12Z Datasheet(PDF) 11 Page - Intersil Corporation |
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CP82C59A-12Z Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 22 page  11 FN2784.5 March 17, 2006 Operation Command Words (OCWs) After the Initialization Command Words (lCWs) are programmed into the 82C59A, the device is ready to accept interrupt requests at its input lines. However, during the 82C59A operation, a selection of algorithms can command the 82C59A to operate in various modes through the Operation Command Words (OCWs). Operation Command Word 1 (OCW1) OCW1 sets and clears the mask bits in the Interrupt Mask Register (lMR) M7 - M0 represent the eight mask bits. M = 1 indicates the channel is masked (inhibited), M = 0 indicates the channel is enabled. Operation Command Word 2 (OCW2) R, SL, EOI - These three bits control the Rotate and End of Interrupt modes and combinations of the two. A chart of these combinations can be found on the Operation Command Word Format. L2, L1, L0 - These bits determine the interrupt level acted upon when the SL bit is active. Operation Command Word 3 (OCW3) ESMM - Enable Special Mask Mode. When this bit is set to 1 it enables the SMM bit to set or reset the Special Mask Mode. When ESMM = 0, the SMM bit becomes a “don’t care”. SMM - Special Mask Mode. If ESMM = 1 and SMM = 1, the 82C59A will enter Special Mask Mode. If ESMM = 1 and SMM = 0, the 82C59A will revert to normal mask mode. When ESMM = 0, SMM has no effect. Fully Nested Mode This mode is entered after initialization unless another mode is programmed. The interrupt requests are ordered in priority from 0 through 7 (0 highest). When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus. Additionally, a bit of the Interrupt Service register (IS0 - 7) is set. This bit remains set until the microprocessor issues an End of Interrupt (EOI) command immediately before returning from the service routine, or if the AEOI (Automatic End of Interrupt) bit is set, until the trailing edge of the last INTA. While the IS bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels will generate an interrupt (which will be acknowledged only if the microprocessor internal interrupt enable flip-flop has been re-enabled through software). After the initialization sequence, IR0 has the highest priority and IR7 the lowest. Priorities can be changed, as will be explained in the rotating priority mode or via the set priority command. OPERATION COMMAND WORDS (OCWs) A0 D7 D6 D5 D4 D3 D2 D1 D0 OCW1 1 M7M6 M5M4M3M2M1M0 OCW2 0 R SL EOI 0 0 L2 L1 L0 OCW3 0 0 ESMM SMM 0 1 P RR RIS 82C59A 82C59A |
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