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SN75ALS1177NE4 Datasheet(PDF) 7 Page - Texas Instruments |
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SN75ALS1177NE4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 14 page SN75ALS1177, SN75ALS1178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS154B – MARCH 1993 – REVISED FEBRUARY 2001 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RECEIVER SECTION electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2‡ V Vhys Input hysteresis voltage (VIT+ – VIT–) 50 mV VIK Enable input clamp voltage SN75ALS1177 II = –18 mA –1.5 V VOH High-level output voltage VID = 200 mV, IOH = –400 µA, See Figure 2 2.7 V VOL Low-level output voltage VID = 200 mV, IOL = 8 mA, See Figure 2 0.45 V IOZ High-impedance-state output current SN75ALS1177 VO = 0.4 V to 2.4 V ±20 µA II Line input current (see Note 6) Other input at 0 V VI = 12 V 1 mA II Line input current (see Note 6) Other input at 0 V VI = –7 V –0.8 mA IIH High-level input current, RE SN75ALS1177 VIH = 2.7 V 20 µA IIL Low-level input current, RE SN75ALS1177 VIL = 0.4 V –100 µA ri Input resistance 12 k Ω IOS Short-circuit output current VO = 0 V, See Note 7 –15 –85 mA ICC Supply current (total package) No load, Outputs enabled 35 50 mA † All typical values are at VCC = 5 V and TA = 25°C. ‡ The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode output and threshold voltage levels only. NOTES: 6. Refer to TIA/EIA-422-B, TIA/EIA-423-A, and TIA/EIA-485-A for exact conditions. 7. Not more than one output should be shorted at a time. switching characteristics at VCC = 5 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output CL = 15 pF, See Figure 6 15 25 37 ns tPHL Propagation delay time, high- to low-level output CL = 15 pF, See Figure 6 15 25 37 ns tPZH Output enable time to high level SN75ALS1177 CL = 100 pF, See Figure 7 10 20 30 ns tPZL Output enable time to low level SN75ALS1177 CL = 100 pF, See Figure 7 10 20 30 ns tPHZ Output disable time from high level SN75ALS1177 CL = 15 pF, See Figure 7 3.5 12 16 ns tPLZ Output disable time from low level SN75ALS1177 CL = 15 pF, See Figure 7 5 12 16 ns |
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