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P82B96P Datasheet(PDF) 2 Page - Texas Instruments |
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P82B96P Datasheet(HTML) 2 Page - Texas Instruments |
2 / 26 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) P82B96 DUAL BIDIRECTIONAL BUS BUFFER SCPS144A – MAY 2006 – REVISED SEPTEMBER 2006 One of the advantages of the P82B96 is that it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus or remote I2C nodes are not apparent to other I2C buses (or nodes). This device also adds minimal loading to I2C node where it is positioned. Any restrictions on the number of I2C devices in a system, or the physical separation between them, are virtually eliminated. The P82B96 easily can transmit SDA/SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (optocoupling), because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be connected directly (without causing bus latching), to provide an alternative bidirectional signal line with I2C properties. Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration. Bidirectional I2C signals do not allow any direction control pin so, instead, slightly different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A regular I2C low applied at the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a regular I2C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation, such as the PCA9515A. The Sx/Sy side is intended only for, and compatible with, the normal I2C logic voltage levels of I2C master and slave devices or Tx/Rx signals of a second P82B96, if required. The Tx/Rx and Ty/Ry I/O pins use the standard I2C logic voltage levels of all I2C parts. If Rx and Tx are connected, Sx can function as either the SDA or SCL line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices. TERMINAL FUNCTIONS NO. NAME DESCRIPTION 1 Sx Serial data bus or SDA. Connect to VCC of I2C master through a pullup resistor. 2 Rx Receive signal. Connect to VCC of P82B96 through a pullup resistor. 3 Tx Transmit signal. Connect to VCC of P82B96 through a pullup resistor. 4 GND Ground 5 Ty Transmit signal. Connect to VCC of P82B96 through a pullup resistor. 6 Ry Receive signal. Connect to VCC of P82B96 through a pullup resistor. 7 Sy Serial clock bus or SCL. Connect to VCC of I2C master through a pullup resistor. 8 VCC Supply voltage 2 Submit Documentation Feedback |
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