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PCA9546A Datasheet(PDF) 7 Page - Texas Instruments |
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PCA9546A Datasheet(HTML) 7 Page - Texas Instruments |
7 / 28 page www.ti.com Data Output by Transmitter SCL From Master Start Condition S 1 2 8 9 Data Output by Receiver Clock Pulse for ACK NACK ACK A A S 1 1 1 0 A2 A1 A0 0 Start Condition SDA R/W ACK From Slave ACK From Slave P B0 B1 B2 B3 X X X X Stop Condition Slave Address Control Register A NA S 1 1 1 0 A2 A1 A0 1 SDA P B3 B2 B1 B0 Start Condition R/W ACK From Slave NACK From Master Stop Condition Slave Address Control Register 0 0 0 0 PCA9546A 4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006 The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA line before the receiver can send an ACK bit. When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7). Setup and hold times must be taken into account. Figure 7. Acknowledgment on the I2C Bus Data is transmitted to the PCA9546A control register using the write mode shown in Figure 8. Figure 8. Write Control Register Data is read from the PCA9546A control register using the read mode shown in Figure 9. Figure 9. Read Control Register 7 Submit Documentation Feedback |
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