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PCA9554ADGV Datasheet(PDF) 5 Page - Texas Instruments |
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PCA9554ADGV Datasheet(HTML) 5 Page - Texas Instruments |
5 / 33 page www.ti.com SDA SCL Start Condition S Stop Condition P SDA SCL Data Line Stable; Data Valid Change of Data Allowed PCA9554A REMOTE 8-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS SCPS127A – SEPTEMBER 2006 – REVISED FEBRUARY 2007 A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). Any number of data bytes can be transferred from the transmitter to receiver between the Start and Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver will signal an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. Figure 1. Definition of Start and Stop Conditions Figure 2. Bit Transfer 5 Submit Documentation Feedback |
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