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PCA9546ADGVT Datasheet(PDF) 10 Page - Texas Instruments

Part # PCA9546ADGVT
Description  4-CHANNEL I2C AND SMBus SWITCH WITH RESET FUNCTION
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCA9546ADGVT Datasheet(HTML) 10 Page - Texas Instruments

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I2C Interface Timing Requirements
Switching Characteristics
Interrupt and Reset Timing Requirements
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
SCPS148D – OCTOBER 2005 – REVISED OCTOBER 2006
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)
STANDARD MODE
FAST MODE
I2C BUS
I2C BUS
UNIT
MIN
MAX
MIN
MAX
fscl
I2C clock frequency
0
100
0
400
kHz
tsch
I2C clock high time
4
0.6
µs
tscl
I2C clock low time
4.7
1.3
µs
tsp
I2C spike time
50
50
ns
tsds
I2C serial-data setup time
250
100
ns
tsdh
I2C serial-data hold time
0(1)
0(1)
µs
ticr
I2C input rise time
1000
20 + 0.1Cb(2)
300
ns
ticf
I2C input fall time
300
20 + 0.1Cb(2)
300
ns
tocf
I2C output fall time
10-pF to 400-pF bus
300
20 + 0.1Cb(2)
300
ns
tbuf
I2C bus free time between stop and start
4.7
1.3
µs
tsts
I2C start or repeated start condition setup
4.7
0.6
µs
tsth
I2C start or repeated start condition hold
4
0.6
µs
tsps
I2C stop condition setup
4
0.6
µs
tvdL(Data)
Valid-data time (high to low)(3)
SCL low to SDA output low valid
1
1
µs
tvdH(Data)
Valid-data time (low to high)(3)
SCL low to SDA output high valid
0.6
0.6
µs
ACK signal from SCL low
tvd(ack)
Valid-data time of ACK condition
1
1
µs
to SDA output low
Cb
I2C bus capacitive load
400
400
pF
(1)
A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), in order to
bridge the undefined region of the falling edge of SCL.
(2)
Cb = total bus capacitance of one bus line in pF
(3)
Data taken using a 1-k
Ω pullup resistor and 50-pF load (see Figure 10)
over recommended operating free-air temperature range, C
L ≤ 100 pF (unless otherwise noted) (see Figure 10)
FROM
TO
PARAMETER
MIN
MAX
UNIT
(INPUT)
(OUTPUT)
RON = 20 Ω, CL = 15 pF
0.3
tpd(1)
Propagation delay time
SDA or SCL
SDn or SCn
ns
RON = 20 Ω, CL = 50 pF
1
(1)
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tWL
Pulse duration, RESET low
6
ns
trst(1)
RESET time (SDA clear)
500
ns
tREC(STA)
Recovery time from RESET to start
0
ns
(1)
trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of tWL.
10
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