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CS80C286-20 Datasheet(PDF) 5 Page - Intersil Corporation |
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CS80C286-20 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 60 page  5 M/IO 67 O MEMORY I/O SELECT: distinguishes memory access from I/O access. If HIGH during TS, a mem- ory cycle or a halt/shutdown cycle is in progress. If LOW, an I/O cycle or an interrupt acknowledge cycle is in progress. M/IO is held at high impedance to the last valid logic state during bus hold ac- knowledge. COD/lNTA 66 O CODE/INTERRUPT ACKNOWLEDGE: distinguishes instruction fetch cycles from memory data read cycles. Also distinguishes interrupt acknowledge cycles from I/O cycles. COD/lNTA is held at high impedance to the last valid logic state during bus hold acknowledge. Its timing is the same as M/IO. LOCK 68 O BUS LOCK: indicates that other system bus masters are not to gain control of the system bus for the current and following bus cycles. The LOCK signal may be activated explicitly by the “LOCK” instruction prefix or automatically by 80C286 hardware during memory XCHG instructions, interrupt acknowledge, or descriptor table access. LOCK is active LOW and is held at a high impedance logic one during bus hold acknowledge. READY 63 l BUS READY: terminates a bus cycle. Bus cycles are extended without limit until terminated by READY LOW. READY is an active LOW synchronous input requiring setup and hold times relative to the system clock be met for correct operation. READY is ignored during bus hold acknowledge. (See Note 1) HOLD HLDA 64 65 I O BUS HOLD REQUEST AND HOLD ACKNOWLEDGE: control ownership of the 80C286 local bus. The HOLD input allows another local bus master to request control of the local bus. When control is granted, the 80C286 will float its bus drivers and then activate HLDA, thus entering the bus hold ac- knowledge condition. The local bus will remain granted to the requesting master until HOLD be- comes inactive which results in the 80C286 deactivating HLDA and regaining control of the local bus. This terminates the bus hold acknowledge condition. HOLD may be asynchronous to the sys- tem clock. These signals are active HIGH. Note that HLDA never floats. INTR 57 I INTERRUPT REQUEST: requires the 80C286 to suspend its current program execution and service a pending external request. Interrupt requests are masked whenever the interrupt enable bit in the flag word is cleared. When the 80C286 responds to an interrupt request, it performs two interrupt acknowledge bus cycles to read an 8-bit interrupt vector that identifies the source of the interrupt. To ensure program interruption, INTR must remain active until an interrupt acknowledge bus cycle is initiated. INTR is sampled at the beginning of each processor cycle and must be active HIGH at least two processor cycles before the current instruction ends in order to interrupt before the next instruction. INTR is level sensitive, active HIGH, and may be asynchronous to the system clock. NMI 59 l NON-MASKABLE INTERRUPT REQUEST: interrupts the 80C286 with an internally supplied vector value of two. No interrupt acknowledge cycles are performed. The interrupt enable bit in the 80C286 flag word does not affect this input. The NMI input is active HIGH, may be asynchronous to the sys- tem clock, and is edge triggered after internal synchronization. For proper recognition, the input must have been previously LOW for at least four system clock cycles and remain HIGH for at least four system clock cycles. PEREQ PEACK 61 6 l O PROCESSOR EXTENSION OPERAND REQUEST AND ACKNOWLEDGE: extend the memory management and protection capabilities of the 80C286 to processor extensions. The PEREQ input requests the 80C286 to perform a data operand transfer for a processor extension. The PEACK out- put signals the processor extension when the requested operand is being transferred. PEREQ is ac- tive HIGH. PEACK is active LOW and is held at a high impedance logic one during bus hold acknowledge. PEREQ may be asynchronous to the system clock. BUSY ERROR 54 53 l I PROCESSOR EXTENSION BUSY AND ERROR: indicates the operating condition of a processor extension to the 80C286. An active BUSY input stops 80C286 program execution on WAIT and some ESC instructions until BUSY becomes inactive (HIGH). The 80C286 may be interrupted while waiting for BUSY to become inactive. An active ERROR input causes the 80C286 to perform a pro- cessor extension interrupt when executing WAIT or some ESC instructions. These inputs are active LOW and may be asynchronous to the system clock. Pin Descriptions The following pin function descriptions are for the 80C286 microprocessor. (Continued) SYMBOL PIN NUMBER TYPE DESCRIPTION 80C286 |
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