HS-82C37ARH_00 datasheet(10/21 Pages) INTERSIL

Part #	HS-82C37ARH

Description	Radiation Hardened CMOS High Performance Programmable DMA Controller

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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10

HS-82C37ARH 42 LEAD CERAMIC FLATPACK

STATIC CONFIGURATION

NOTES:

15. VDD = +6.0V

±5%Part is Static Sensitive

16. TA = 125

oC MinimumVoltage Must be Ramped

17. Resistors:

R1 = 10k

Ω±10% (Pins 6, 7, 11-13, 16-19)

R2 = 2.7k

Ω±5% (Pins 1, 2, 21-23, 26-30, 32-36)

START-UP TIMING

NOTES:

18. F0 is 50% duty cycle square wave pulse burst.

19. 1.0kHz

≤ F0 ≤ 100kHzF0 is left High after pulse burst

20. 10 cycles

≤ F0 Pulse Burst ≤ 1.0s

21. F1 = Single pulse with width equal to 2 cycles of F0

22. F1 is left Low after pulse burst

23. F1 pulse occurs after start of F0 and ends before F0.

Input levels: 0.9VDD

≤ VIH ≤ VDD, -0.3V ≤ VIL ≤ 0.7V

DYNAMIC CONFIGURATION

NOTES:

24. VDD = 6.5V

±5% (Burn-In)

25. VDD = 6.0V

±5% (Life Test)

26. TA = 125

oC Minimum

27. Part is Static Sensitive, Voltage Must be Ramped

28. Resistors:

R1 = 10k

Ω±10% (Pins 6, 7, 11-13, 16-19)

R2 = 2.7k

Ω±10% (Pins 1, 2, 21-23, 26-30, 32-36, and LOADS)

Burn-In Circuits (Continued)

VDD

1

2

3

4

5

6

7

8

9

21

13

10

11

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16

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19

20

37

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35

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28

29

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36

26

23

24

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22

27

F0

F1

LOAD

2.7k

Ω

2.7k

Ω

VDD

1

2

3

4

5

6

7

8

9

21

13

10

11

12

14

15

16

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18

19

20

37

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42

35

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32

31

28

29

30

36

26

23

24

25

22

27

F0

LOAD

F0

F5

F1

F2

F3

F4

LOAD

OPEN

VDD

LOAD

F5

F4

F3

F2

F1

F0

F1

HS-82C37ARH

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