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LCL7104-16CPL Datasheet(PDF) 10 Page - Intersil Corporation |
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LCL7104-16CPL Datasheet(HTML) 10 Page - Intersil Corporation |
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10 / 19 page  10 Buffer Gain At the end of the auto-zero interval, the instantaneous noise voltage on the auto-zero capacitor is stored, and subtracts from the input voltage while adding to the reference voltage during the next cycle. The result is that this noise voltage effectively is somewhat greater than the input noise voltage of the buffer itself during integration. By introducing some voltage gain into the buffer, the effect of the auto-zero noise (referred to the input) can be reduced to the level of the inherent buffer noise. This generally occurs with a buffer gain of between 3 and 10. Further increase in buffer gain merely increases the total offset to be handled by the auto-zero loop, and reduces the available buffer and integrator swings, without improving the noise per- formance of the system. The circuit recommended for doing this with the ICL8068/ICL7104 is shown in Figure 7. With care- ful layout, the circuit shown can achieve effective input noise voltages on the order of 1 to 2 µV, allowing full 16-bit use with full scale inputs of a low as 150mV. Note that at this level, ther- moelectric EMFs between PC boards, IC pins, etc., due to local temperature changes can be very troublesome. For further dis- cussion, see Application Note AN030. ICL8052 vs ICL8068 The ICL8052 offers significantly lower input leakage currents than the ICL8068, and may be found preferable in systems with high input impedances. However, the ICL8068 has substantially lower noise voltage, and for systems where system noise is a limiting factor, particularly in low signal level conditions, will give better performance. Component Value Selection For optimum performance of the analog section, care must be taken in the selection of values for the integrator capaci- tor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to suit the particular application. FIGURE 6D. PHASE III DEINTEGRATE A2 + - A3 + - INTEGRATOR COMP. A1 + - BUFFER CINT 1 RINT CAZ ZERO CROSS. DET. POL CL 2 3 6 7 8 9 -AN I/P CL ZERO CROSSING F/F Q D VREF CREF - + 4 TABLE 3. THREE-STATE BYTE FORMATS AND ENABLE PINS CE/LD HBEN MBEN LBEN ICL7104-16 POL O/R B16 B15 B14 B13 B12 B11 B10 B9B8B7B6B5B4B3B2B1 HBEN LBEN ICL7104-14 POL O/R B14 B13 B12 B11 B10 B9B8B7B6B5B4B3B2B1 TABLE 4. TYPICAL COMPONENT VALUES (V++ = +15V, V+ = 5V, V- = 5V, V- = -15V, fCLOCK = 200kHz) ICL8052/8068 WITH ICL7104-16 ICL7104-14 UNIT Full scale VIN 200 800 4000 100 4000 mV Buffer Gain 10 1 1 10 1 V/V RINT 100 43 200 47 180 k Ω CINT 0.33 0.33 0.33 0.1 0.1 µF CAZ 11111 µF CREF 10 1 1 10 1 µF VREF 100 400 2000 50 2000 mV Resolution 3.1 12 61 6.1 244 µV ICL7104 |
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