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AD7541 Datasheet(PDF) 3 Page - Intersil Corporation

Part # AD7541
Description  12-Bit, Multiplying D/A Converter
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

AD7541 Datasheet(HTML) 3 Page - Intersil Corporation

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Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC
transfer function from a “best fit straight line” function.
Normally expressed as a percentage of full scale range. For
a multiplying DAC, this should hold true over the entire VREF
range.
Resolution: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of LSB = (VREF)/2
N. A
bipolar converter of N bits has a resolution of
LSB = (VREF)/2
(N-1). Resolution in no way implies linearity.
Settling Time: Time required for the output function of the
DAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
Gain Error: Ratio of the DAC’s operational amplifier output
voltage to the nominal input voltage value.
Feedthrough Error: Error caused by capacitive coupling
from VREF to output with all switches OFF.
Output Capacitance: Capacitance from IOUT1, and IOUT2
terminals to ground.
Output Leakage Current: Current which appears on
IOUT1, terminal when all digital inputs are LOW or on IOUT2
terminal when all inputs are HIGH.
Detailed Description
The AD7541 is a 12-bit, monolithic, multiplying D/A converter.
A highly stable thin film R-2R resistor ladder network and
NMOS SPDT switches form the basis of the converter circuit.
CMOS level shifters provide low power TTL/CMOS
compatible operation. An external voltage or current reference
and an operational amplifier are all that is required for most
voltage output applications. A simplified equivalent circuit of
the DAC is shown on page 1, (Functional Diagram). The
NMOS SPDT switches steer the ladder leg currents between
IOUT1 and IOUT2 buses which must be held at ground
potential. This configuration maintains a constant current in
each ladder leg independent of the input code. Converter
errors are further eliminated by using wider metal
interconnections between the major bits and the outputs. Use
of high threshold switches reduces the offset (leakage) errors
to a negligible level.
Each circuit is laser-trimmed, at the wafer level, to better
than 12-bits linearity. For the first four bits of the ladder,
special trim-tabbed geometries are used to keep the body of
the resistors, carrying the majority of the output current,
undisturbed. The resultant time stability of the trimmed
circuits is comparable to that of untrimmed units.
DIGITAL INPUTS
Low State Threshold, VIL
(Notes 2, 6)
-
-
0.8
-
0.8
V
High State Threshold, VIH
2.4
-
-
2.4
-
V
Input Current
VIN = 0V or V+ (Note 6)
-
-
±1-
±1
µA
Input Coding
See Tables 1 and 2 (Note 6)
Binary/Offset Binary
Input Capacitance
(Note 6)
-
-
8
-
8
pF
POWER SUPPLY CHARACTERISTICS
Power Supply Voltage Range
Accuracy Is Not Guaranteed Over
This Range
+5 to +16
V
I+
All Digital Inputs High or Low
(Excluding Ladder Network)
-
-
2.0
-
2.5
mA
Total Power Dissipation
(Including Ladder Network)
-
20
-
-
-
mW
NOTES:
2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic
fields. Keep unused units in conductive foam at all times.
3. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK.
4. Full scale range (FSR) is 10V for unipolar and
±10V for bipolar modes.
5. Using internal feedback resistor, RFEEDBACK.
6. Guaranteed by design or characterization and not production tested.
7. Accuracy not guaranteed unless outputs at ground potential.
Electrical Specifications
V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = 25
oC, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TA = 25
oCT
A MIN-MAX
UNITS
MIN
TYP
MAX
MIN
MAX
AD7541


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