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AD7541JN Datasheet(PDF) 5 Page - Intersil Corporation |
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AD7541JN Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 8 page 5 A “Logic 1” input at any digital input forces the corresponding ladder switch to steer the bit current to IOUT1 bus. A “Logic 0” input forces the bit current to IOUT2 bus. For any code the IOUT1 and IOUT2 bus currents are complements of one another. The current amplifier at IOUT2 changes the polarity of IOUT2 current and the transconductance amplifier at IOUT1 output sums the two currents. This configuration doubles the output range of the DAC. The difference current resulting at zero offset binary code, (MSB = “Logic 1”, All other bits = “Logic 0”), is corrected by using an external resistive divider, from VREF to IOUT2. Offset Adjustment 1. Adjust VREF to approximately +10V. 2. Set R4 to zero. 3. Connect all digital inputs to “Logic 1”. 4. Adjust IOUT1 amplifier offset zero adjust trimpot for 0V ±0.1mV at I OUT2 amplifier output. 5. Connect a short circuit across R2. 6. Connect all digital inputs to “Logic 0”. 7. Adjust IOUT2 amplifier offset zero adjust trimpot for 0V ±0.1mV at IOUT1 amplifier output. 8. Remove short circuit across R2. 9. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”. 10. Adjust R4 for 0V ±0.2mV at V OUT . Gain Adjustment 1. Connect all digital inputs to VDD. 2. Monitor VOUT for a -VREF (1 - 1/ 2 11) volts reading. 3. To increase VOUT, connect a series resistor, (0Ω to 250 Ω), in the IOUT1 amplifier feedback loop. 4. To decrease VOUT, connect a series resistor, (0Ω to 250 Ω), between the reference voltage and the VREF terminal. TABLE 2. CODE TABLE - BIPOLAR (OFFSET BINARY) OPERATION DIGITAL INPUT ANALOG OUTPUT 111111111111 -VREF (1 - 1/ 2 11) 100000000001 -VREF ( 1/ 2 11) 100000000000 0 011111111111 VREF ( 1/ 2 11) 000000000001 VREF (1 - 1/ 2 11) 000000000000 VREF IOUT2 6 6 IOUT1 17 18 1 4 15 3 2 AD7541 BIT 1 (MSB) BIT 12 (LSB) 16 +15V VREF DIGITAL INPUT ±10V R1 10K R5 10K VOUT - + A1 - + A2 GND R2 10K R3 390K R4 500 Ω NOTE: R1 and R2 should be 0.01%, low-TCR resistors. FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) AD7541 |
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