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AD7541KN Datasheet(PDF) 4 Page - Intersil Corporation

Part # AD7541KN
Description  12-Bit, Multiplying D/A Converter
Download  8 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

AD7541KN Datasheet(HTML) 4 Page - Intersil Corporation

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4
The level shifter circuits are comprised of three inverters with
a positive feedback from the output of the second to first
(Figure 1). This configuration results in TTL/COMS
compatible operation over the full military temperature
range. With the ladder SPDT switches driven by the level
shifter, each switch is binary weighted for an “ON” resistance
proportional to the respective ladder leg current. This
assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder resistor,
resulting in accurate leg currents.
Typical Applications
General Recommendations
Static performance of the AD7541 depends on IOUT1 and
IOUT2 (pin 1 and pin 2) potentials being exactly equal to
GND (pin 3).
The output amplifier should be selected to have a low input
bias current (typically less than 75nA), and a low drift
(depending on the temperature range). The voltage offset of
the amplifier should be nulled (typically less than
±200µV).
The bias current compensation resistor in the amplifier’s
non-inverting input can cause a variable offset. Non-
inverting input should be connected to GND with a low
resistance wire.
Ground-loops must be avoided by taking all pins going to
GND to a common point, using separate connections.
The V+ (pin 16) power supply should have a low noise level
and should not have any transients exceeding +17V.
Unused digital inputs must be connected to GND or V+ for
proper operation.
A high value resistor (~1M
Ω) can be used to prevent static
charge accumulation, when the inputs are open-circuited for
any reason.
When gain adjustment is required, low tempco
(approximately 50ppm/oC) resistors or trim-pots should be
selected.
Unipolar Binary Operation
The circuit configuration for operating the AD7541 in
unipolar mode is shown in Figure 2. With positive and
negative VREF values the circuit is capable of 2-Quadrant
multiplication. The “Digital Input Code/Analog Output Value”
table for unipolar mode is given in Table 1. A Schottky diode
(HP5082-2811 or equivalent) prevents IOUT1 from negative
excursions which could damage the device. This precaution
is only necessary with certain high speed amplifiers.
Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V
±0.5mV (Max) at V
OUT .
Gain Adjustment
1. Connect all digital inputs to VDD.
2. Monitor VOUT for a -VREF (1 -
1/
2
12) reading.
3. To increase VOUT , connect a series resistor, (0Ω to
250
Ω), in the IOUT1 amplifier feedback loop.
4. To decrease VOUT, connect a series resistor, (0Ω to
250
Ω), between the reference voltage and the V
REF
terminal.
Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7541 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage
values Four-Quadrant multiplication can be realized. The
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.
V+
TTL/CMOS
INPUT
13
4
5
6
7
2
89
TO LADDER
IOUT2 IOUT1
FIGURE 1. CMOS LEVEL SHIFTER AND SWITCH
TABLE 1. CODE TABLE - UNIPOLAR BINARY OPERATION
DIGITAL INPUT
ANALOG OUTPUT
111111111111
-VREF (1 -
1/
2
12)
100000000001
-VREF (
1/
2 +
1/
2
12)
100000000000
-VREF/2
011111111111
-VREF (
1/
2 -
1/
2
12)
000000000001
-VREF (
1/
2
12)
000000000000
0
17
18
1
4
15
3
2
AD7541
BIT 1 (MSB)
BIT 12 (LSB)
16
+15V
VREF
GND
IOUT1
IOUT2
VOUT
-
+
RFEEDBACK
DIGITAL
INPUT
CR1
5
±10V
A
FIGURE 2. UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION)
AD7541


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