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LAN91C100FD_0601 Datasheet(PDF) 4 Page - SMSC Corporation |
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LAN91C100FD_0601 Datasheet(HTML) 4 Page - SMSC Corporation |
4 / 78 page FEAST Fast Ethernet Controller with Full Duplex Capability Rev. 01-20-06 Page 4 SMSC DS – LAN91C100FD Rev. D DATASHEET Figure 5.7 - Drive Send and Allocate Routines ............................................................................................................49 Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU ....................................................................................52 Figure 6.1 - 64 X 16 Serial EEPROM Map ...................................................................................................................55 Figure 7.1 - LAN91C100FD on VL BUS.......................................................................................................................58 Figure 7.2 - LAN91C100FD on ISA Bus.......................................................................................................................60 Figure 7.3 - LAN91C100FD on EISA Bus ....................................................................................................................63 Figure 9.1 - Asynchronous Cycle - nADS=0.................................................................................................................67 Figure 9.2 - Asynchronous Cycle - Using nADS...........................................................................................................68 Figure 9.3 - Asynchronous Cycle - nADS=0.................................................................................................................69 Figure 9.4 - Burst Write Cycles - nVLBUS=1 ...............................................................................................................70 Figure 9.5 - Burst Read Cycles - nVLBUS=1 ...............................................................................................................71 Figure 9.6 - Address Latching for all Modes.................................................................................................................72 Figure 9.7 - Synchronous Write Cycles - nVLBUS=0 ...................................................................................................72 Figure 9.8 - Synchronous Read Cycle - NVLBUS=0 ....................................................................................................73 Figure 9.9 - SRAM Interface ........................................................................................................................................74 Figure 9.10 - ENDEC Interface - 10 Mbps ...................................................................................................................75 Figure 9.11 - MII Interface............................................................................................................................................76 Figure 10.1 - 208 Pin QFP Package Outline ................................................................................................................77 Figure 10.2 - 208 Pin TQFP Package Outlines ............................................................................................................78 LIST OF TABLES Table 3.1 - LAN91C100FD Pin Requirements 12 Table 5.1 - Internal I/O Space Mapping 22 Table 7.1 - VL Local Bus Signal Connections 56 Table 7.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors 59 Table 7.3 - EISA 32 Bit Slave Signal Connections 61 Table 10.1 - 208 Pin QFP Package Parameters 77 Table 10.2 - 208 Pin TQFP Package Outlines 78 |
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