Philips Semiconductors

Product specification

N-channel enhancement mode

IRFZ24N

TrenchMOS

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel

enhancement

mode

SYMBOL

PARAMETER

MAX.

UNIT

standard level field-effect power

transistor in a plastic envelope using

V

DS

Drain-source voltage

55

V

’trench’ technology. The device

I

D

Drain current (DC)

17

A

features very low on-state resistance

P

tot

Total power dissipation

45

W

and has integral zener diodes giving

T

j

Junction temperature

175

˚C

ESD protection up to 2kV. It is

R

DS(ON)

Drain-source on-state

70

m

Ω

intended for use in switched mode

resistance

V

power supplies and general purpose

switching applications.

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

tab

drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

-

-

55

V

V

DGR

Drain-gate voltage

R

-55

V

±V

GS

Gate-source voltage

-

-

20

V

I

D

Drain current (DC)

T

-

17

A

I

D

Drain current (DC)

T

-

12

A

I

DM

Drain current (pulse peak value)

T

-

68

A

P

tot

Total power dissipation

T

-

45

W

T

Storage & operating temperature

-

- 55

175

˚C

ESD LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

C

Electrostatic discharge capacitor

Human body model

-

2

kV

voltage, all pins

(100 pF, 1.5 k

Ω)

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R

th j-mb

Thermal resistance junction to

-

-

3.3

K/W

mounting base

R

th j-a

Thermal resistance junction to

in free air

60

-

K/W

ambient

d

g

s

12 3

tab

February 1999

1

Rev 1.000