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ICM7211AM Datasheet(PDF) 4 Page - Intersil Corporation |
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ICM7211AM Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 8 page 4 FN3158.7 April 17, 2006 Input Definitions In this table, V DD and VSS are considered to be normal operating input logic levels. Actual input low and high levels are specified under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply. INPUT DIP TERMINAL CONDITIONS FUNCTION B0 27 VDD = Logical One VSS = Logical Zero Ones (Least Significant) Data Input Bits B1 28 VDD = Logical One VSS = Logical Zero Twos B2 29 VDD = Logical One VSS = Logical Zero Fours B3 30 VDD = Logical One VSS = Logical Zero Eights (Most Significant) OSC 36 Floating or with External Capacitor to VDD Oscillator Input VSS Disables BP output devices, allowing segments to be synchronized to an external signal input at the BP terminal (Pin 5). Interface Input Configuration INPUT DESCRIPTION DIP TERMINAL CONDITIONS FUNCTION DA1 Digit Address Bit 1 (LSB) 31 VDD = Logical One VSS = Logical Zero DA1 and DA2 serve as a 2-bit Digit Address Input DA2, DA1 = 00 selects D4 DA2, DA1 = 01 selects D3 DA2, DA1 = 10 selects D2 DA2, DA1 = 11 selects D1 DA2 Digit Address Bit 2 (MSB) 32 VDD = Logical One VSS = Logical Zero CS1 Chip Select 1 33 VDD = Inactive VSS = Active When both CS1 and CS2 are taken low, the data at the Data and Digit Select code inputs are written into the input latches. On the rising edge of either Chip Select, the data is decoded and written into the output latches. CS2 Chip Select 2 34 VDD = Inactive VSS = Active Timing Diagram FIGURE 1. MICROPROCESSOR INTERFACE INPUT CS1 (CS2) CS2 (CS1) DATA AND DIGIT ADDRESS = DON’T CARE tDH tDS tWI tICS ICM7211AM ICM7211AM |
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