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HS0-9008RH-Q Datasheet(PDF) 4 Page - Intersil Corporation |
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HS0-9008RH-Q Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 4 page 4 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3279.4 March 10, 2005 Die Characteristics DIE DIMENSIONS: 180 mils x 197 mils x 21 ±1 mils INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8k Å ±1kÅ Top Metallization: Metal 1 - Type: Moly/TiW Thickness: 5.8k Å ±10% Metal 2- Type: Al/Si/Cu Thickness: 10k Å ±10% Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential (Powered Up): VDD ADDITIONAL INFORMATION: Worst Case Current Density: Metal 1 - Designs using the Intersil AVLSI-1RA process take advantage of the superior current carrying capabilities of Moly.TiW. The current density limit established by Intersil Reliability is 5.0 x 105 A/cm2 Metal 2 - 1.63 x 105 A/cm2 Process: AVLSI1RA Metallization Mask Layout HS-9008RH HS-9008RH |
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