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AM29LV641MH101FI Datasheet(PDF) 11 Page - Advanced Micro Devices |
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AM29LV641MH101FI Datasheet(HTML) 11 Page - Advanced Micro Devices |
11 / 60 page December 21, 2005 Am29LV641MH/L 9 DA TA SH EET DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Device Bus Operations Legend: L = Logic Low = V IL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, A IN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0. Sector addresses are A21:A15. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection and Unprotection” section. 3. If WP# = V IL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.) 4. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2). VersatileIO ™ (V IO) Control The VersatileIO™ (V IO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on VIO. See “Ordering Informa- tion” on page 8 for VIO options on this device. For example, a VI/O of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 V devices on the same data bus. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid Operation CE# OE# WE# RESET# WP# ACC Addresses (Note 2) DQ0– DQ15 Read L L H H XL/H A IN D OUT Write (Program/Erase) L H L H (Note 3) L/H A IN (Note 4) Accelerated Program L H L H (Note 3) V HH A IN (Note 4) Standby V CC ± 0.3 V XX V CC ± 0.3 V XH XHigh-Z Output Disable L H H H XL/H XHigh-Z Reset X X X L XL/H XHigh-Z Sector Group Protect (Note 2) L H L V ID HL/H SA, A6 =L, A3=L, A2=L, A1=H, A0=L (Note 4) Sector Group Unprotect (Note 2) LH L V ID HL/H SA, A6=H, A3=L, A2=L, A1=H, A0=L (Note 4) Temporary Sector Group Unprotect XX X V ID HL/H A IN (Note 4) |
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