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AM49DL320BGT851T Datasheet(PDF) 5 Page - Advanced Micro Devices |
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AM49DL320BGT851T Datasheet(HTML) 5 Page - Advanced Micro Devices |
5 / 64 page 4 Am49DL320BG June 25, 2002 P R E L I M I NARY Figure 32. Pseudo SRAM Write Cycle— UB#s and LB#s Control................................................................... 58 Flash Erase And Programming Performance . . . 59 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 59 Package Pin Capacitance . . . . . . . . . . . . . . . . . . 59 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 59 pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 60 pSRAM Power on and Deep Power Down . . . . . 60 Figure 33. Deep Power-down Timing.............................................. 60 Figure 34. Power-on Timing........................................................... 60 pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 61 Figure 35. Read Address Skew ..................................................... 61 Figure 36. Write Address Skew...................................................... 61 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62 FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 62 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63 |
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