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HSP50110JC-52 Datasheet(PDF) 4 Page - Intersil Corporation |
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HSP50110JC-52 Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 25 page  4 Functional Description The Digital Quadrature Tuner (DQT) provides many of the functions needed for digital demodulation including: carrier LO generation, mixing, low-pass filtering, baseband sampling, baseband AGC, and IF AGC error detection. A block diagram of the DQT is provided in Figure 1. The DQT processes a real or complex input at rates up to 52 MSPS. The digitized IF is input to the Synthesizer/Mixer where it is multiplied by a quadrature LO of user programmable frequency. This operation tunes the channel of interest to DC where it is extracted by the Low Pass FIR Filtering section. The filter bandwidth is set through a user programmable decimation factor. The decimation factor is set by the Re- Sampler which controls the baseband sampling rate. The baseband sample rate can be adjusted by an external symbol tracking loop via a serial interface. Similarly, a serial interface is provided which allows the frequency of the Synthesizer/Mixer’s NCO to be controlled by an external carrier tracking loop. The serial interfaces were designed to mate with the output of loop filters on the HSP50210 Digital Costas Loop. The DQT provides an input level detector and an internal AGC to help maintain the input and output signal magnitudes at user specified levels. The input level detector compares the input signal magnitude to a programmable level and generates an error signal. The error signal can be externally averaged to set the gain of an amplifier in front of the A/D which closes the AGC loop. The output signal level is maintained by an internal AGC loop closed around the Low Pass Filtering. The AGC loop gain and gain limits are programmable. Input Controller The input controller sets the input sample rate of the processing elements. The controller has two operational modes which include a Gated Input Mode for processing sample rates slower than CLK, and an Interpolated Input Mode for increasing the effective time resolution of the samples. The mode is selected by setting bit 1 of the I/O Formatting Control Register in Table 9. In Gated Input Mode, the Input Enable (ENI) controls the data flow into the input pipeline and the processing of the internal elements. When this input is sampled “low” by CLK, the data on IIN0-9 and QIN0-9 is clocked into the processing pipeline; when ENI is sampled “high”, the data inputs are disabled. The Input Enable is pipelined to the internal processing elements so that they are enabled once for each time ENI is sampled low. This mode minimizes the COMPLEX MULTIPLIER LEVEL DETECT F O R M A T LEVEL DETECT LOOP FILTER RE-SAMPLER SYNTHESIZER SHIFT REG MICROPROCESSOR INTERFACE COS SIN IIN0-9 QIN0-9 HI/LO PH0-1 COF SOF CFLD COFSYNC SOFSYNC WR RD C0-7 10 10 CENTER PHASE 32 8 SAMPLER CENTER 32 AGC THRESHOLD † THRESHOLD FOR LOWER LIMIT † UPPER LIMIT † LOOP GAIN † 10 10 12 12 11 11 10 10 IOUT0-9 QOUT0-9 DECIMATING COMPENSATION FILTER FILTER † Indicates data downloaded via microprocessor interface SSTRB SPH0-4 5 ENI SYNTHESIZER/MIXER SHIFT REG RE-SAMPLER DIVIDER LOW PASS FILTERING AGC EXTERNAL AGC † NCO NCO FREQUENCY † FREQUENCY † OEI DATARDY OEQ CLK CLK A0-2 FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF HSP50110 LOTP HI/LO OUTPUT SENSE † INPUT MODE † INPUT FORMAT † COF EN † WORD WIDTH † SOF EN † WORD WIDTH † OFFSET † HSP50110 |
Similar Part No. - HSP50110JC-52 |
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Similar Description - HSP50110JC-52 |
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