©1993 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74ABT573 Rev. 1.4

2

Connection Diagram

Pin Descriptions

Functional Description

The ABT573 contains eight D-type latches with 3-STATE

output buffers. When the Latch Enable (LE) input is

condition the latches are transparent, i.e., a latch output

will change state each time its D input changes. When

LE is LOW the latches store the information that was

present on the D inputs a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE buffers are

controlled by the Output Enable (OE) input. When OE is

LOW, the buffers are in the bi-state mode. When OE is

HIGH the buffers are in the high impedance mode but

this does not interfere with entering new data into the

latches.

Function Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

Pin Names

Descriptions

Data Inputs

LE

Latch Enable Input (Active HIGH)

OE

3-STATE Output Enable Input

(Active LOW)

3-STATE Latch Outputs

Inputs

Outputs

OE

LE

D

O

LH

H

H

LH

L

L

LL

X

HX

X

Z