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2

Unit Loading/Fan Out

Functional Description

The 74F821 consists of ten D-type edge-triggered flip-

flops. This device has 3-STATE true outputs for bus sys-

tems organized in a broadside pinning. The buffered Clock

(CP) and buffered Output Enable (OE) are common to all

flip-flops. The flip-flops will store the state of their individual

D inputs that meet the setup and hold times requirements

on the LOW-to-HIGH CP transition. With the OE LOW the

content of the flip-flops are available at the outputs. When

the OE is HIGH, the outputs go to the high impedance

state. Operation of the OE input does not affect the state of

the flip-flops.

Function Table

L

= LOW Voltage Level

H

= HIGH Voltage Level

X

= Immaterial

Z

= High Impedance

 = LOW-to-HIGH Transition

NC

= No Change

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

Data Inputs

1.0/1.0

20

µA/−0.6 mA

OE

Output Enable

1.0/1.0

20

µA/−0.6 mA

3-STATE Input

CP

Clock Input

1.0/1.0

20

µA/−0.6 mA

3-STATE Outputs

150/40 (33.3)

−3.0 mA/24 mA (20 mA)

Inputs

Internal Output

Function

OE

CP

D

Q

O

H

H

X

NC

Z

Hold

H

L

X

NC

Z

Hold

H



L

H

Z

Load

H



H

L

Z

Load

L



L

H

L

Data Available

L



H

L

H

Data Available

L

H

X

NC

NC

No Change in Data

L

L

X

NC

NC

No Change in Data