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HIP6004DCBZ Datasheet(PDF) 8 Page - Intersil Corporation |
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HIP6004DCBZ Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 14 page 8 FN4855.3 July 13, 2005 Figure 5 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 5 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the HIP6004D within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the HIP6004D must be sized to handle up to 1A peak current. Figure 6 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS pin and locate the capacitor, CSS close to the SS pin because the internal current source is only 10 μA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse- width modulated (PWM) wave with an amplitude of VIN at the PHASE node. TABLE 1. OUTPUT VOLTAGE PROGRAM PIN NAME NOMINAL OUTPUT VOLTAGE DACOUT PIN NAME NOMINAL OUTPUT VOLTAGE DACOUT VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 11 111 0 0 111 1 1.475 11 110 1.100 0 111 0 1.500 11 101 1.125 0 110 1 1.525 11 100 1.150 0 110 0 1.550 11 011 1.175 0 101 1 1.575 11 010 1.200 0 101 0 1.600 11 001 1.225 0 100 1 1.625 11 000 1.250 0 100 0 1.650 10 111 1.275 0 011 1 1.675 10 110 1.300 0 011 0 1.700 10 101 1.325 0 010 1 1.725 10 100 1.350 0 010 0 1.750 10 011 1.375 0 001 1 1.775 10 010 1.400 0 001 0 1.800 10 001 1.425 0 000 1 1.825 10 000 1.450 0 000 0 1.850 NOTE: 0 = connected to GND or VSS, 1 = connected to VDD through pull-up resistors. PGND LO CO LGATE UGATE PHASE Q1 Q2 D2 VIN VOUT RETURN HIP6004D CIN FIGURE 5. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES +12V HIP6004D SS GND VCC BOOT D1 LO CO VOUT Q1 Q2 PHASE +VIN CBOOT CVCC CSS HIP6004D |
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