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ISL5217KIZ Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL5217KIZ Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 43 page 5 FN6004.3 July 8, 2005 TXENA, TXENB, TXENC, TXEND I Transmit Enable A-D. (TXENX) The processing channel selected for this enable will force a channel flush (conditioned by control word 0x0c, bit 2), clear the data RAMs, and update the selected configuration registers upon assertion. No additional requests for serial data will be made when TXENX is deasserted, unless conditioned by control word 0x0c, bit 3. The polarity of TXENX is programmable. Optionally, TXENX can be internally generated with a programmable duty cycle. Two different programmable TXENX cycles can be programmed and toggled between based on programmed cycle length. See control word 0x0c, bit 11 and Table 43 for additional details. UPDA, UPDB, UPDC, UPDD I Update A-D. (UPDX) The processing channel selected for this input updates the selected configuration registers, if the associated update mask bit is set. The polarity of UPDX is programmable. SYNCO O Synchronization Output. The processing of multiple ISL5217 devices can be synchronized through software by connecting the SYNCO of the master ISL5217 device to an UPDX pin of the ISL5217 slaves. The polarity of SYNCO is programmable. MODULATED DATA (80) IOUT(19:0) O Output Data Bus A (19:0). Output bus A contains the digital modulated QUC output samples from Output Summer/Formatter 1. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB. QOUT(19:0) O Output Data Bus B (19:0). The output bus contains the digital modulated QUC output samples from Output Summer/Formatter 2. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB. IIN(19:0) I/O I Cascade In (19:0) or OUTPUT BUS C. Dual function I/O bus. The bus is configured for input when the output mode is cascade in. The bus is configured for output for all other output modes. I Cascade In. Input bus allows multiple parts to be cascaded by routing the digital modulated signal I CAS OUT, (Bus A), from one QUC into Output Summer/Formatter 1 of a second QUC. I CAS IN (19:0) is in 2’s complement format and is sampled on the rising edge of CLK. Bit<19> is the MSB. Output Data Bus C. The output bus contains the digital modulated QUC output samples from Output Summer/Formatter 3. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB. QIN(19:0) I/O Q Cascade in (19:0) or Output Data Bus D. Dual function I/O bus. The bus is configured for input when the output mode is cascade in. The bus is configured for output for all other output modes. Q Cascade in. Input bus allows multiple parts to be cascaded by routing the digital modulated signal Q CAS OUT, (Bus B), from one QUC into Output Summer/Formatter 2 of a second QUC. Q CAS IN (19:0) is in 2’s complement format and is sampled on the rising edge of CLK. Bit<19> is the MSB. Output Data Bus D. The output bus contains the digital modulated QUC output samples from Output Summer/Formatter 4. The samples are updated on the rising edge of the CLK. Bit <19> is the MSB. ISTRB O I data strobe. (active high). Used in the muxed I/Q mode. When asserted, the output data buses contain valid I data. JTAG TEST ACCESS PORT TMS I JTAG Test Mode Select. Internally pulled up. TDI I JTAG Test Data In. Internally pulled up. TCK I JTAG Test Clock. TRST I JTAG Test Reset (Active Low). Internally pulled-up. This pin should be driven by the JTAG logic to obtain a TAP controller reset, or if JTAG is not utilized, this pin should be tied to ground for normal operation. As recommended in the 1149.1 standard documentation the TRST test pin should be made active soon after power-up to guarantee a known state within the TAP logic on the ISL5217. This avoids potential damage due to signal contention at the circuit’s inputs and outputs. TDO O JTAG Test Data Out. Pin Descriptions (all signals are active high unless otherwise stated) (Continued) NAME TYPE DESCRIPTION ISL5217 |
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