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ISL59481IRZ-T13 Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL59481IRZ-T13 Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 12 page  8 FN6208.3 December 22, 2006 Pin Equivalent Circuits Figure 15A illustrates the optimum output load for testing AC performance. Figure 15B illustrates the optimum output load when connecting to 50 Ω input terminated equipment. Application Information General The ISL59481 is ideal as the matrix element of high performance switchers and routers. Key features include high impedance buffered analog inputs and excellent AC performance at output loads down to 150 Ω for video cable- driving. The unity-gain current feedback output amplifiers are stable operating into capacitive loads and bandwidth is optimized with a load of 5pF in parallel with a 500 Ω. Total output capacitance can be split between the PCB capacitance and an external load capacitor. Ground Connections For the best isolation and crosstalk rejection, all GND pins must connect to the GND plane. Power-up Considerations The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT-triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply rates-of-rise in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 16) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. One Schottky can be used to protect both V+ power supply pins, and a second for the protection of both V- pins. IN V+ V- LOGIC PIN V+ V- GND 33k 21k + - 1.2V V+ V- OUT CIRCUIT 3 CIRCUIT 2 CIRCUIT 1 V1- ~1M Ω SUBSTRATE 1 V1- V1+ GNDB1 CAPACITIVELY COUPLED ESD CLAMP GNDC1 GNDA1 V2- V2+ GNDB2 CAPACITIVELY COUPLED ESD CLAMP GNDC2 GNDA2 CIRCUIT 4B CIRCUIT 4A THERMAL HEAT SINK PAD V2- ~1M Ω SUBSTRATE 2 AC Test Circuits FIGURE 15A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD FIGURE 15B. TEST CIRCUIT FOR MEASURING WITH 50 Ω OR 75 Ω INPUT TERMINATED EQUIPMENT FIGURE 15C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500Ω WILL BE DEGRADED. FIGURE 15. TEST CIRCUITS ISL59481 CL 50 Ω VIN 500 Ω RL 5pF or 75 Ω ISL59481 RS CL VIN 475 Ω TEST 5pF 50 Ω or 75 Ω 50 Ω or 75 Ω 50 Ω or 75 Ω EQUIPMENT ISL59481 RS CL VIN 50 Ω or 75Ω TEST 5pF 50 Ω or 75 Ω 50 Ω or 75 Ω EQUIPMENT ISL59481 |
Similar Part No. - ISL59481IRZ-T13 |
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