11

www.fairchildsemi.com

FCAS50SN60 Rev. A

Note:

1. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s

printed circuit board. The input signal section integrates 3.3k

Ω(typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the signal

voltage drop at input terminal.

2. The logic input is compatible with standard CMOS or LSTTL outputs.

Figure 10. Recommended CPU I/O Interface Circuit

Note:

Figure 11. Recommended Bootstrap Operation Circuit and Parameters

CPU

COM

5V-Line

1nF

Ω

4.7k

V

FO

Ω

100

1nF

SRM Module

R

C

IN

(H)

IN

(L)

15V-Line

25Ω

18uF

0.1uF

1000uF

1uF

SRM module

Vcc

IN

COM

VB

HO

VS

Vcc

IN

COM

OUT

Outputs

P

N

A

This Value depends on PW M Control Algorithm

D

BS

R

BS

V

SL

N

B

RE(H)=10Ω