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ISL6210CRZ-T Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6210CRZ-T Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 10 page 7 FN6392.0 November 28, 2006 During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 1V threshold, at which time the UGATE is released to rise. Adaptive shoot-through circuitry monitors the upper MOSFET gate-to-source voltage during UGATE turn-off. Once the upper MOSFET gate-to-source voltage has dropped below a threshold of 1V, the LGATE is allowed to rise. In addition to gate threshold monitoring, a programmable delay between MOSFET switching can be accomplished by placing a resistor in series with the FCCM input. This delay allows for maximum design flexibility over MOSFET selection. The delay can be programmed from 5ns to 50ns and is obtained from the absolute value of the current flowing into the FCCM pin. If no resistor is used, the minimum 5ns delay is selected. Gate threshold monitoring is not affected by the addition or removal of the additional dead-time. Refer to Figure 2 and Figure 3 for more detail. The equation governing the dead-time seen in Figure 3 is expressed as: The equation can be rewritten to solve for RDELAY as follows: Internal Bootstrap Diode This driver features an internal bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The following equation helps select a proper bootstrap capacitor size: where QG1 is the amount of gate charge per upper MOSFET at VGS1 gate-source voltage and NQ1 is the number of control MOSFETs. The ΔV BOOT_CAP term is defined as the allowable droop in the rail of the upper gate drive. As an example, suppose two IRLR7821 FETs are chosen as the upper MOSFETs. The gate charge, QG, from the data sheet is 10nC at 4.5V (VGS) gate-source voltage. Then the QGATE is calculated to be 22nC at PVCC level. We will assume a 200mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.110 μF is required. The next larger standard value 1V FCCM = VCC or GND GATE A GATE B 1V FCCM = RESISTOR to VCC or GND TDELAY = 5n - 50ns GATE A GATE B FIGURE 2. PROGRAMMABLE DEAD-TIME ADAPTIVE PROTECTION WITH DELAY ADAPTIVE SHOOT-THROUGH PROTECTION 50 45 40 35 30 25 20 15 10 5 0 0 167 667 333 500 833 1000 RDELAY (kΩ) tDELAY FIGURE 3. ISL6210 PROGRAMMABLE DEAD-TIME vs DELAY RESISTOR T DELAY ns () 0.045 R DELAY k Ω () × [] 5ns + = (EQ. 1) R DELAY kΩ () T DELAY ns () 5ns – () 0.045 ------------------------------------------------------ = (EQ. 2) C BOOT_CAP Q GATE ΔV BOOT_CAP -------------------------------------- ≥ Q GATE Q G1 PVCC • V GS1 ------------------------------------ N Q1 • = (EQ. 3) ISL6210 |
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