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OM4031T Datasheet(PDF) 7 Page - NXP Semiconductors |
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OM4031T Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 16 page October 1994 7 Philips Semiconductors Preliminary specification Digital post-detection filter for FSK data receivers OM4031T OPERATING INSTRUCTIONS Control signals The operation of the OM4031T is determined by 3 control signals (CE, A0 and A1) and the clock frequency at input CLK. Table 1 shows the various possibilities for a typical clock frequency of 38.4 kHz. The parameter N is the number of samples used in the calculation of the average bit value. The parameter fs is the input sampling frequency, assuming a 38.4 kHz external clock signal. The logic levels on A0 and A1 can be changed while CE = HIGH, except to select or deselect 2400 bits/s with doubled bandwidth (A1 = LOW, A0 = HIGH). This mode must be entered or left while CE = LOW to avoid data errors on DOUT. Table 1 Data rate and filter bandwidth selection Note 1. At 4800 bits/s the oversampling rate is 8. CE A1 A0 N (samples) fs (kHz) DATA RATE (bits/s) NORMAL BANDWIDTH DOUBLE BANDWIDTH 0X X X X X X 1 0 0 12 9.6 600 − 1 1 0 12 19.2 1200 600 1 0 1 6 38.4 4800(1) 2400 1 1 1 12 38.4 2400 1200 Power-down mode To reduce power consumption the filter can be disabled by applying a LOW level to input CE. The result is as follows: • The internal clock is inhibited • Output DOUT is made 3-state and static. Reset The OM4031T is reset internally when power-down mode is left by applying a HIGH level to input CE. The actual reset takes place on the second falling edge on input CLK after CE = HIGH. The status after reset is as follows: • The shift register contains a 101010... pattern • DOUT is made LOW. After power-up input CE must be kept at a LOW level for at least one clock period on input CLK. This ensures a successful reset when CE is made HIGH. |
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