8

The heart of the controller is an input direct summing

comparator which sum voltage feedback, current feedback,

slope compensation ramp and power tracking signals

together. Slope compensation is required to prevent system

instability that occurs in current-mode topologies operating

at duty-cycles greater than 50% and is also used to define

the open-loop gain of the overall system. The slope

compensation is fixed internally and optimized for 500mA

inductor ripple current. The power tracking will not contribute

any input to the comparator steady-state operation. Current

feedback is measured by the patented sensing scheme that

senses the inductor current flowing through the high-side

switch whenever it is conducting. At the beginning of each

oscillator period the high-side NMOS switch is turned on.

The comparator inputs are gated off for a minimum period of

time of about 150ns (LEB) after the high-side switch is

turned on to allow the system to settle. The Leading Edge

Blanking (LEB) period prevents the detection of erroneous

voltages at the comparator inputs due to switching noise. If

the inductor current exceeds the maximum current limit

the feedback voltage FB derived from the regulator output

reference voltage. The resultant error voltage is summed

with the current feedback and slope compensation ramp.

The high-side switch remains on until all four comparator

inputs have summed to zero, at which time the high-side

switch is turned off and the low-side switch is turned on.

However, the maximum on-duty ratio of the high-side switch

is limited to 95%. In order to eliminate cross-conduction of

the high-side and low-side switches a 15ns break-before-

make delay is incorporated in the switch drive circuitry. The

output enable (EN) input allows the regulator output to be

disabled by an external logic control signal.

Output Voltage Setting

In general:

However, due to the relatively low open loop gain of the

system, gain errors will occur as the output voltage and loop-

gain is changed. This is shown in the performance curves. A

in the event that FB is floating.

NMOS Power FETs and Drive Circuitry

The EL7562 integrates low on-resistance (60m

Ω) NMOS

FETs to achieve high efficiency at 2A. In order to use an

NMOS switch for the high-side drive it is necessary to drive

the gate voltage above the source voltage (LX). This is

and diode. When the low-side switch is turned on and the LX

beginning of the next cycle the high-side switch turns on and

Reference

A 1.5% temperature compensated bandgap reference is

as the dominant pole of the amplifier and can be increased

in size to maximize transient noise rejection. A value of

0.1µF is recommended.

Oscillator

The system clock is generated by an internal relaxation

oscillator with a maximum duty-cycle of approximately 95%.

or can be driven by an external source. If the oscillator is

driven by an external source care must be taken in selecting

gain of the system.

When external synchronization is required, always choose

lower than that of sync source to accommodate component

and temperature variations. Figure 1 shows a typical

connection.

0.985

1

-------

+

⎝⎠

⎜⎟

⎛⎞

×

=

0.975

1

-------

+

⎝⎠

⎜⎟

⎛⎞

×

=

FIGURE 1. OSCILLATOR SYNCHRONIZATION

2

3

11

10

9

6

7

8

15

14

EL7562

1

16

External

Oscillato

BAT54

100p