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OQ2536HP Datasheet(PDF) 7 Page - NXP Semiconductors

Part # OQ2536HP
Description  SDH/SONET STM16/OC48 demultiplexer
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

OQ2536HP Datasheet(HTML) 7 Page - NXP Semiconductors

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1998 Mar 10
7
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
FUNCTIONAL DESCRIPTION
The OQ2536HP is a 32-channel demultiplexer, intended
for use in STM16/OC48 applications. It demultiplexes a
single 2.5 Gbits/s input channel to 32
× 78 Mbits/s output
channels.
The demultiplexing is performed in two stages.
The 2.5 Gbits/s data channel is first demultiplexed to four
622 Mbits/s data channels. Each of these channels is then
fed to a 1 : 8 demultiplexer to generate 32
× 78 Mbits/s
output channels.
The ENL control input is used for switching between
normal and loop modes. When loop mode is enabled
(ENL = LOW), inputs DLOOP, DLOOPQ, CLOOP and
CLOOPQ are selected. In normal mode (ENL = HIGH),
inputs DIN, DINQ, CIN and CINQ are selected.
The signal applied to CIN and CINQ is a 2.5 GHz
recovered clock signal, e.g. coming from the OQ2541 data
and clock recovery IC. The clock is divided down to
78 MHz, which is used for receive logic timing and is
available as a GTL compatible output at pin CDIV.
High bit rate stage: 1 : 4 DMUX
The 2.5 Gbits/s data stream is fed into a 1 : 4
demultiplexer to generate four 622 Mbits/s channels.
The input pins DIN, DINQ, DLOOP, DLOOPQ, CIN, CINQ,
CLOOP and CLOOPQ are terminated internally with 50
resistors to GND.
Low bit rate part: 4
× 1 : 8 DMUX
The four 622 Mbits/s output channels coming from the
high bit rate stage are loaded into four 8-bit shift registers.
The 622 MHz clock for these shift registers comes from the
preceding stage.
The 32 bits contained in the shift registers are loaded into
latches and made available on outputs D0 to D31. These
outputs are 1.2 V GTL compatible and have internal 100
pull up resistors. The 78 MHz clock output, CDIV, has an
internal 50
Ω pull up resistor.
The first serial data bit coming in at DIN or DLOOP is given
out at pin D31 (MSB) and so on.
The data outputs may not always represent four STM
bytes. This is because the internal load pulse for the output
latches is not synchronized to the STM16 frame.
Power supply connections
The power supply pins need to be individually decoupled
using chip capacitors mounted as close as possible to the
IC. If multiple decoupling capacitors are used for a single
supply node, large distance between the capacitances
should be avoided in order to avoid resonance.
To minimize low frequency switching noise in the vicinity of
the OQ2536HP, all power supply lines should be filtered
once by an LC-circuit with a low cutoff frequency
(as shown in the application diagram, Fig.7).
Ground connection
The ground connection on the PCB needs to be a large
copper area fill connected to a common ground plane with
low inductance.
RF connections
A coupled stripline or microstrip with an odd mode
characteristic impedance of 50
Ω (nominal value) should
be used for the RF connections on the PCB.
The connections should be kept as short as possible. This
applies to the CML differential line pairs CIN and CINQ,
DIN and DINQ, CLOOP and CLOOPQ, and DLOOP and
DLOOPQ. In addition, the following lines should not vary in
length by more than 5 mm:
• CIN, CINQ, DIN and DINQ
• DLOOP, DLOOPQ, CLOOP and CLOOPQ.
Interface to receive logic
The 78 Mbits/s interface lines, CDIV and D0 to D31,
should not exceed 50 mm in length. The parasitic
capacitance of these lines should be as small as possible
(less than 3 pF is desirable).
ESD protection
All pads are protected by ESD protection diodes, with the
exception of the high frequency inputs DIN, DINQ,
DLOOP, DLOOPQ, CIN, CINQ, CLOOP and CLOOPQ.
Cooling
In many cases it is necessary to mount a special cooling
device on the package. The thermal resistance from
junction to case, Rth j-c and from junction to ambient, Rth j-a,
are given in Chapter “Thermal characteristics”. Since the
heat-slug in the package is connected to the die, the
cooling device should be electrically isolated.
To calculate if a heatsink is necessary, the maximum
allowed total thermal resistance R is calculated as:
(1)
R
th
T
j
T
amb
P
tot
------------------------
=


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