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P80CL580 Datasheet(PDF) 9 Page - NXP Semiconductors

Part # P80CL580
Description  Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P80CL580 Datasheet(HTML) 9 Page - NXP Semiconductors

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1997 Mar 14
9
Philips Semiconductors
Product specification
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
P80CL580; P83CL580
P0.0 to P0.7
37 to 44
37 to 44
• Port 0: 8-bit open-drain bidirectional I/O port. As an open-drain output
port it can sink 8 LS TTL loads. Port 0 pins that have logic 1s written
to them float, and in that state will function as high impedance inputs.
• Low-order addressing: Port 0 is also the multiplexed low-order
address and data bus during access to external memory. The strong
internal pull-ups are used while emitting logic 1s within the low order
address.
P2.0 to P2.7
55 to 53,
49 to 45
56 to 54,
49 to 45
• Port 2: 8-bit bidirectional I/O port with internal pull-ups.
Same characteristics as Port 4.
• High-order addressing: Port 2 emits the high-order address byte
during accesses to external memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses the strong internal
pull-ups when emitting logic 1s. During accesses to external memory
that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the
P2 Special Function Register.
EA
50
51
External Access. When EA is held HIGH the CPU executes out of
internal Program Memory (unless the program counter exceeds
17FFH). Holding EA LOW forces the CPU to execute out of external
memory regardless of the value of the Program Counter.
ALE
51
52
Address Latch Enable. Output pulse for latching the low byte of the
address during access to external memory. ALE is emitted at a constant
rate of 1
6 × fosc, and may be used for external timing or clocking
purposes (assuming MOVX instructions are not used).
PSEN
52
53
Program Store Enable. Output read strobe to external Program
Memory. When executing code out of external Program Memory, PSEN
is activated twice each machine cycle. However, during each access to
external Data Memory two PSEN activations are skipped.
VDD
56
57
Power supply.
n.c.
3, 9, 17, 18,
35, 36, 50
and 58
Not connected.
SYMBOL
PIN
DESCRIPTION
VSO56
QFP64


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