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X28HC64P-70 Datasheet(PDF) 4 Page - Intersil Corporation |
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X28HC64P-70 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 17 page 4 FN8109.1 June 7, 2006 PIN DESCRIPTIONS Addresses (A0-A12) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power con- sumption is reduced. Output Enable (OE) The Output Enable input controls the data output buff- ers and is used to initiate read operations. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28HC64 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28HC64. PIN NAMES BLOCK DIAGRAM Symbol Description A0-A12 Address Inputs I/O0-I/O7 Data Input/Output WE Write Enable CE Chip Enable OE Output Enable VCC +5V VSS Ground NC No Connect X Buffers Latches and Decoder I/O Buffers and Latches Y Buffers Latches Decoder Control Logic and Timing 65,536-Bit EEPROM Array I/O0–I/O7 Data Inputs/Outputs CE OE VCC VSS A0–A12 WE Address Inputs and X28HC64 |
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