X40020S14Z-B datasheet(3/24 Pages) INTERSIL

Part #	X40020S14Z-B

Description	Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch

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Manufacturer	INTERSIL [Intersil Corporation]

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FN8112.1

May 17, 2006

Low VCC detection circuitry protects the user’s system

from low voltage conditions, resetting the system

when VCC falls below the minimum VTRIP1 point.

RESET/RESET is active until VCC returns to proper

operating level and stabilizes. A second voltage moni-

tor circuit tracks the unregulated supply to provide a

power fail warning or monitors different power supply

voltage. Three common low voltage combinations are

available. However, Intersil’s unique circuits allows the

threshold for either voltage monitor to be repro-

grammed to meet specific system level requirements

or to fine-tune the threshold for applications requiring

higher precision.

A manual reset input provides debounce circuitry for

minimum reset component count.

A battery switch circuit compares VCC with VBATT input

and connects VOUT to whichever is higher. This pro-

vides voltage to external SRAM or other circuits in the

event of main power failure. The X40020/21 can drive

50mA from VCC to 250µA from VBATT. The device only

switches to VBATT when VCC drops below the low VCC

voltage threshold and VBATT.

The Watchdog Timer provides an independent protec-

tion mechanism for microcontrollers. When the micro-

controller fails to restart a timer within a selectable

time out interval, the device activates the WDO signal.

The user selects the interval from three preset values.

Once selected, the interval does not change, even

after cycling the power.

The device features an 2-wire interface and software

protocol allowing operation on a two-wire bus.

The device utilizes Intersil’s proprietary Direct Write™

cell, providing a minimum endurance of 100,000

cycles and a minimum data retention of 100 years.

PIN CONFIGURATION

VBATT

VSS

VCC

SDA

SCL

3

2

4

1

12

13

11

14

LOWLINE

WDO

RESET

7

6

5

8

9

10

V2MON

MR

WP

3

2

4

1

12

13

11

14

7

6

5

8

9

10

VOUT

BATT-ON

V2FAIL

VBATT

VCC

SDA

SCL

WP

VOUT

BATT-ON

VSS

LOWLINE

WDO

RESET

V2MON

MR

V2FAIL

X40020

X40021

14-Pin SOIC, TSSOP

PIN DESCRIPTION

Name

Function

1V2FAIL

V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and

goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.

2V2MON

V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes

LOW. This input can monitor an unregulated power supply with an external resistor divider or can

monitor a second power supply with no external components. Connect V2MON to VSS or VCC when

not used.

3LOWLINE

Early Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1.

When

VCC > VTRIP1, this pin is pulled high with the use of an external pull up resistor.

4WDO

WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog

timer goes active.

5MR

Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will

remain HIGH/LOW until the pin is released and for the tPURST thereafter. It has an internal pull up

resistor.

6

RESET/

RESET

RESET Output. (X40021) This open drain pin is an active LOW output which goes LOW whenever

VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-

grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and

for tPURST thereafter.

RESET Output. (X40020) This pin is an active HIGH open drain output which goes HIGH whenever

VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-

grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and

for tPURST thereafter.

X40020, 40021

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