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X4003S8I-4.5A Datasheet(PDF) 7 Page - Intersil Corporation

Part # X4003S8I-4.5A
Description  CPU Supervisor
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X4003S8I-4.5A Datasheet(HTML) 7 Page - Intersil Corporation

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7
FN8113.1
May 11, 2006
Figure 4. VTRIP Programming Sequence
Control Register
The control register provides the user a mechanism
for changing the watchdog timer settings. watchdog
timer bits are nonvolatile and do not change when
power is removed.
The control register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh.
It can only be modified by performing a control register
write operation. Only one data byte is allowed for each
register write operation. Prior to writing to the control reg-
ister, the WEL and RWEL bits must be set using a two
step process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register" below.
The user must issue a stop after sending the control
byte to the register to initiate the nonvolatile cycle that
stores WD1 and WD0. The X4003/X4005 will not
acknowledge any data bytes written after the first byte
is entered.
The state of the control register can be read at any
time by performing a serial read operation. Only one
byte is read by each register read operation. The
X4003/X4005 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
VTRIP Programming
Apply 5V to VCC
Decrement VCC
RESET pin
goes active?
Measured VTRIP -
Desired VTRIP
DONE
Execute
Sequence
Reset VTRIP
Set VCC = VCC Applied =
Desired VTRIP
Execute
Sequence
Set VTRIP
New VCC Applied =
Old VCC applied + Error
(VCC = VCC - 50mV)
Execute
Sequence
Reset VTRIP
New VCC Applied =
Old VCC Applied - Error
Error
≤ –Emax
-Emax < Error < Emax
YES
NO
Error
≥ Emax
Emax = Maximum Allowable VTRIP Error
7
6543
2
1
0
0WD1 WD0
0
0
RWEL
WEL
0
X4003, X4005


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