4

FN8113.1

May 11, 2006

PIN CONFIGURATION

PIN DESCRIPTION

NC

SDA

SCL

3

2

4

1

6

7

5

8

NC

WP

RESET

8-Pin JEDEC SOIC, MSOP

Pin

(SOIC/DIP)

Pin

TSSOP

Pin

(MSOP)

Name

Function

1

3

NC

No internal connections

2

4

NC

No internal connections

3

5

2

RESET/

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open

RESET goes active if the watchdog timer is enabled and SDA re-

mains either HIGH or LOW longer than the selectable Watchdog

time out period. A falling edge of SDA, while SCL also toggles from

HIGH to LOW followed by a stop condition

resets the watchdog timer. RESET/RESET goes active on power-

up and remains active for 250ms after the power supply stabilizes.

46

3

Ground

57

4

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into

and out of the device. It has an open drain output and may be wire

ORed with other open drain or open collector outputs. This pin re-

quires a pull up resistor and the input buffer is

always active (not gated).

Watchdog Input. A HIGH to LOW transition on the SDA while

SCL also toggles from HIGH to LOW follow by a stop condition re-

sets the watchdog timer. The absence of this procedure within the

watchdog time out period results in RESET/RESET going active.

68

5

SCL

Serial Clock. The serial clock controls the serial bus timing for

data input and output.

71

6

WP

Write Protect. WP HIGH prevents changes to the watchdog

timer setting.

82

1

Supply voltage

X4003, X4005