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X4163V8IZ-2.7 Datasheet(PDF) 11 Page - Intersil Corporation |
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X4163V8IZ-2.7 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 22 page  11 FN8120.1 May 12, 2006 Figure 8. Byte Write Sequence Serial Write Operations BYTE WRITE For a write operation, the device requires the Slave Address Byte and a Word Address Byte. This gives the master access to any one of the words in the array. After receipt of the Word Address Byte, the device responds with an acknowledge, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, the device again responds with an acknowledge. The master then terminates the trans- fer by generating a stop condition, at which time the device begins the internal write cycle to the nonvola- tile memory. During this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 8. A write to a protected block of memory will suppress the acknowledge bit. Page Write The device is capable of a page write operation. It is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the device will respond with an acknowl- edge, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on the same page. This means that the master can write 64 bytes to the page starting at any location on that page. If the master begins writing at location 60, and loads 12-bytes, then the first 4- bytes are written to locations 60 through 63, and the last 8-bytes are written to locations 0 through 7. After- wards, the address counter would point to location 8 of the page that was just written. If the master supplies more than 64-bytes of data, then new data over-writes the previous data, one byte at a time. Figure 9. Page Write Operation S t a r t S t o p Slave Address Word Address Byte 0 Data A C K A C K A C K SDA Bus Signals from the Slave Signals from the Master 0 Word Address Byte 1 A C K 0 1 0 1 S t a r t S t o p Slave Address Word Address Byte 1 Data (n) A C K A C K A C K SDA Bus Signals from the Slave Signals from the Master 0 Data (1) A C K (1 < n < 64) Word Address Byte 0 A C K 1 0 10 X4163, X4165 |
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