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X4163S8-2.7A Datasheet(PDF) 8 Page - Intersil Corporation |
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X4163S8-2.7A Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 22 page  8 FN8120.1 May 12, 2006 read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. BP2, BP1, BP0: Block Protect Bits (Nonvolatile) The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block pro- tect bits will prevent write operations to the following segments of the array. RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the Control Register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part powers up again. Writes to the WEL bit do not cause a nonvolatile write cycle, so the device is ready for the next opera- tion immediately after the stop condition. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the Watchdog Timer. The options are shown below. Write Protect Enable These devices have an advanced Block Lock scheme that protects one of five blocks of the array when enabled. It provides hardware write protection through the use of a WP pin and a nonvolatile Write Protect Enable (WPEN) bit. The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Control Register control the programmable Hardware Write Protect feature. Hard- ware Write Protection is enabled when the WP pin and the WPEN bit are HIGH and disabled when either the WP pin or the WPEN bit is LOW. When the chip is Hardware Write Protected, nonvolatile writes to the block protected sections in the memory array cannot be written and the block protect bits cannot be changed. Only the sections of the memory array that are not block protected can be written. Note that since the WPEN bit is write protected, it cannot be changed back to a LOW state; so write protection is enabled as long as the WP pin is held HIGH. Table 1. Write Protect Enable Bit and WP Pin Function 76 5 4 3 2 1 0 WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2 Protected Addresses (Size) Array Lock 0 0 0 None (factory setting) None 0 0 1 None None 0 1 0 None None 0 1 1 0000h - 7FFh (2K bytes) Full Array (All) 1 0 0 000h - 03Fh (64 bytes) First Page (P1) 1 0 1 000h - 07Fh (128 bytes) First 2 pgs (P2) 1 1 0 000h - 0FFh (256 bytes) First 4 pgs (P4) 1 1 1 000h - 1FFh (512 bytes) First 8 pgs (P8) WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled (factory setting) WP WPEN Memory Array not Block Protected Memory Array Block Protected WPEN Bit Protection LOW X Writes OK Writes Blocked Writes OK Software HIGH 0 Writes OK Writes Blocked Writes OK Software HIGH 1 Writes OK Writes Blocked Writes Blocked Hardware X4163, X4165 |
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