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X28HC256P-12 Datasheet(PDF) 8 Page - Intersil Corporation

Part # X28HC256P-12
Description  5 Volt, Byte Alterable EEPROM
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X28HC256P-12 Datasheet(HTML) 8 Page - Intersil Corporation

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FN8108.1
May 17, 2006
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 6 and 7 for the sequence.
The three-byte sequence opens the page write window,
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle
has been completed, the device will automatically be
returned to the data protected state.
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
Figure 7. Write Sequence for Software Data
Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28HC256 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28HC256 will be
write protected during power-down and after any sub-
sequent power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
CE
WE
(VCC)
Write
Protected
VCC
0V
Data
Address
AAA
5555
55
2AAA
A0
5555
≤ tBLC MAX
Writes
ok
Byte
or
Age
tWC
Write Last
Write Data XX
to Any
Write Data A0
to Address
5555
Write Data 55
to Address
2AAA
Write Data AA
to Address
5555
After tWC
Re-Enters Data
Protected State
Byte to
Last Address
Address
Optional
Byte/Page
Load Operation
Byte/Page
Load Enabled
X28HC256


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