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Delay Capacitance [Cd]

(μF)

(ms)

(ms)

0.01

13.8

11.0 ~ 16.6

0.022

30.4

24.3 ~ 36.4

0.047

64.9

51.9 ~ 77.8

0.1

138

110 ~ 166

0.22

304

243~ 364

0.47

649

519 ~ 778

1

1380

1100 ~ 1660

■

OPERATIONAL EXPLANATION

A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on the next page.

①

As an early state, the input voltage pin is applied sufficiently high voltage to the release voltage and the delay capacitance

②

the delay capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit,

③

While the input pin voltage keeps below the detect voltage, and 0.7V or more, the delay capacitance is discharged to the

④

While the input pin voltage drops to 0.7V or less and it increases again to 0.7V or more, the output voltage may not be

able to maintain the “Low” level. Such an operation is called “Unspecified Operation”, and voltage which occurs at the

⑤

⑥

transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging

via a delay resistor (Rdelay). The internal circuit, which uses the delay capacitance pin as power input, will operate as a

⑦

While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or higher, the

* In = a natural logarithm

The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and

As an example, presuming that the delay capacitance is 0.68μF, TDR is :

* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground

⑧

●

Release Delay Time Chart