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X9251UV24Z Datasheet(PDF) 3 Page - Intersil Corporation |
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X9251UV24Z Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 20 page 3 FN8166.5 April 13, 2007 Circuit Level Applications • Vary the gain of a voltage amplifier • Provide programmable dc reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the dc biasing of a pin diode attenuator in RF circuits • Provide a control variable (I, V, or R) in feedback circuits System Level Applications • Adjust the contrast in LCD displays • Control the power level of LED transmitters in communication systems • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems Pinout X9251 (24 LD SOIC/TSSOP) TOP VIEW Pin Assignments PIN (SOIC) SYMBOL FUNCTION 1 SO Serial Data Output for SPI bus 2 A0 Device Address for SPI bus. (See Note 1) 3RW3 Wiper Terminal of DCP3 4RH3 High Terminal of DCP3 5RL3 Low Terminal of DCP3 7VCC System Supply Voltage 8RL0 Low Terminal of DCP0 9RH0 High Terminal of DCP0 10 RW0 Wiper Terminal of DCP0 11 CS SPI bus. Chip Select active low input 12 WP Hardware Write Protect - active low 13 SI Serial Data Input for SPI bus 14 A1 Device Address for SPI bus. (See Note 1) 15 RL1 Low Terminal of DCP1 16 RH1 High Terminal of DCP1 17 RW1 Wiper Terminal of DCP1 18 VSS System Ground 20 RW2 Wiper Terminal of DCP2 21 RH2 High Terminal of DCP2 22 RL2 Low Terminal of DCP2 23 SCK Serial Clock for SPI bus 24 HOLD Device select. Pauses the SPI serial bus. 6, 19 NC No Connect NOTE: 1. A0 and A1 device address pins must be tied to a logic level. SO A0 RW3 NC VCC RL0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 HOLD SCK RL2 RH2 RW2 NC VSS RW1 RH1 RL1 X9251 RH3 14 13 11 12 RL3 RH0 RW0 CS A1 SI WP X9251 |
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