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X9258UV24-2.7 Datasheet(PDF) 8 Page - Intersil Corporation |
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X9258UV24-2.7 Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 20 page  8 FN8168.4 August 30, 2006 Figure 7. Acknowledge Response from Receiver Figure 8. Detailed Potentiometer Block Diagram Detailed Operation All DCP potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9258 contains four Wiper Counter Registers, one for each DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its data register zero (R0) upon power-up. SCL from Data Output 1 89 START Acknowledge Master from Transmitter Data Output from Receiver Serial Data Path From Interface Circuitry Register 0 Register 1 Register 2 Register 3 Serial BUS Input Parallel BUS Input Wiper Counter Register INC/DEC Logic UP/DN CLK Modified SCL UP/DN VH/RH VL/RL VW/RW If WCR = 00[H] then VW/RW = VL/RL If WCR = FF[H] then VW/RW = VH/RH 8 8 C o u n t e r D e c o d e (WCR) X9258 |
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