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X9410WV24-2.7 Datasheet(PDF) 6 Page - Intersil Corporation |
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X9410WV24-2.7 Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 21 page  6 FN8193.2 October 12, 2006 Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9410; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – Read Wiper Counter Register—read the current wiper position of the selected pot, – Write Wiper Counter Register—change current wiper position of the selected pot, – Read Data Register—read the contents of the selected data register; – Write Data Register—write a new value to the selected data register. – Read Status—This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 5 and Figure 6. The final command is Increment/Decrement. It is different from the other commands because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps, thereby providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 7 and Figure 8. Figure 4. Two-Byte Instruction Sequence Figure 5. Three-Byte Instruction Sequence (Write) Figure 6. Three-Byte Instruction Sequence (Read) 0101 00A1 A0 I3 I2 I1 I0 R1 R0 0 P0 SCK SI CS 0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 0 P0 SCL SI 0 0 D5 D4 D3 D2 D1 D0 CS 00 0 1 0 1 A1 A0 I3 I2 I1 I0 R1 R0 0 P0 SCL SI CS 00 S0 0 0 D5 D4 D3 D2 D1 D0 Don’t Care X9410 |
Similar Part No. - X9410WV24-2.7 |
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Similar Description - X9410WV24-2.7 |
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