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ISL90810 Datasheet(PDF) 4 Page - Intersil Corporation |
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ISL90810 Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 11 page  4 FN8234.2 November 10, 2006 Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX UNITS ICC1 VCC Supply Current (Volatile Write/Read) fSCL = 400kHz; SDA = Open; (for I 2C, Active, Read and Volatile Write States only) 20 100 µA ISB VCC Current (Standby) VCC = +5.5V, I 2C Interface in Standby State, Temperature range from -40°C to +85°C 25 µA VCC = +5.5V, I 2C Interface in Standby State, Temperature range from -40°C to +105°C 28 µA VCC = +3.6V, I 2C Interface in Standby State, Temperature range from -40°C to +85°C 0.8 2 µA VCC = +3.6V, I 2C Interface in Standby State, Temperature range from -40°C to +105°C 0.8 5 µA ILkgDig Leakage Current at Pins SDA and SCL Voltage at pin from GND to VCC -10 10 µA tDCP (Note 14) DCP Wiper Response Time SCL falling edge of last bit of DCP Data Byte to wiper change 1µs Vpor Power-On Recall Voltage Minimum VCC at which memory recall occurs 1.8 2.6 V VCCRamp VCC Ramp Rate 0.2 V/ms tD (Note 14) Power-Up Delay VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state 3ms SERIAL INTERFACE SPECIFICATIONS VIL SDA, and SCL Input Buffer LOW Voltage -0.3 0.3*VCC V VIH SDA, and SCL Input Buffer HIGH Voltage 0.7*VCC VCC+0.3 V Hysteresis (Note 14) SDA and SCL Input Buffer Hysteresis 0.05* VCC V VOL (Note 14) SDA Output Buffer LOW Voltage, Sinking 4mA 00.4 V Cpin (Note 14) SDA, and SCL Pin Capacitance 10 pF fSCL SCL Frequency 400 kHz tIN (Note 14) Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA (Note 14) SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window. 900 ns tBUF (Note 14) Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VCC crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VCC crossing. 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VCC. 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC 100 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. 0ns tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. 600 ns ISL90810 |
Similar Part No. - ISL90810_06 |
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Similar Description - ISL90810_06 |
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