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ISL95711WIU10Z Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL95711WIU10Z Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 13 page 9 FN8241.3 September 5, 2006 Principles of Operation The ISL95711 is an integrated circuit incorporating one DCP with it’s associated register, non-volatile memory, and the I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered-down, the last value stored in the IVR will be maintained in the nonvolatile memory. When power is restored, the contents of the IVR are recalled and the wiper is set to that value. The ISL95711 has dual supplies, VCC and V-. For proper operation of the chip, it is recommended both power supplies ramp up simultaneously to their final values within 20ms. The chip design gives priority to the V- supply stabilization and then looks at VCC stabilization. As the V- supply goes below -2.5V, the RW pin goes to the default code of 64. As VCC also exceeds 2.5V (after V- < -2.5V), the RW pin goes to the code stored in the EEPROM memory value (this is referred as power on recall). DCP Description The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of the DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal is controlled by a 7-bit volatile Wiper Register (WR). When the WR contains all zeroes (00h), the wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR contains all ones (7Fh), the wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (7Fh), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL95711 is being powered up, the WR is reset to 40h (64 decimal), which locates the RW at the center between RL and RH. Soon after the power supply voltage becomes large enough for reliable non-volatile memory reading (~ ±2.5V), the ISL95711 reads the value stored on a non-volatile Initial Value Register (IVR) and loads it into the WR. The WR and IVR can be read or written directly using the I2C serial interface as described in the following sections. Memory Description The ISL95711 contains 1 non-volatile byte know as the Initial Value Register (IVR). It is accessed by the I2C interface operations with Address 00h. The IVR contains the value which is loaded into the Volatile Wiper Register (WR) at power-up. The volatile WR, and the non-volatile IVR of a DCP are accessed with the same address. FIGURE 13. WIPER MOVEMENT FIGURE 14. LARGE SIGNAL SETTLING TIME Typical Performance Curves (Continued) ISL95711 |
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