8

FN8243.1

April 17, 2006

This device supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the

bus as a transmitter and the receiving device as the receiver.

The device controlling the transfer is a master and the

device being controlled is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, this device

operates as a slave device in all applications. All

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (See

Figure 6). On power up, the SDA pin is in the input mode. All

which is a HIGH to LOW transition of SDA while SCL is

HIGH. The device continuously monitors the SDA and SCL

lines for the START condition and does not respond to any

command until this condition is met (See Figure 6). A START

condition is ignored during the power up sequence and

operations must be terminated by a STOP condition, which

is a LOW to HIGH transition of SDA while SCL is HIGH (See

Figure 6). A STOP condition at the end of a Read operation,

or at the end of a Write operation to volatile bytes only

places the device in its standby mode. A STOP condition

during a Write operation to a non-volatile byte, initiates an

internal non-volatile write cycle. The device enters its

standby state when the internal non-volatile write cycle is

completed.

An ACK, Acknowledge, is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (See Figure 7). This device

responds with an ACK after recognition of a START

condition followed by a valid Identification Byte, and once

again after successful receipt of the Address Byte. This

device also responds with an ACK after receiving each Data

Byte of a Write operation. The master must respond with an

ACK after receiving each Data Byte of a read operation

except the last one. A valid Identification Byte contains 1010

as the four MSBs. The following three bits are the MSBs of

the memory address to be accessed. The LSB of the

Identification Byte is the Read/Write bit. Its value is “1” for a

Read operation, and “0” for a Write operation (See Table 2).

The complete memory address location to be accessed is a

11-bit word, since the memory has 2048 bytes. The eight

LSBs are in the Address Byte.

TABLE 2. IDENTIFICATION BYTE FORMAT

10

1

0

A10

A9

A8

R/Wb

MSB

LSB

SCL

SDA

START

STOP

SCL

SDA

DATA STABLE

DATA CHANGE

DATA STABLE

FIGURE 6. VALID DATA CHANGES, START AND STOP CONDITIONS

ISL96017