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ISL95711UIU10Z Datasheet(PDF) 4 Page - Intersil Corporation |
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ISL95711UIU10Z Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 13 page  4 FN8241.3 September 5, 2006 Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX UNITS ICC1 VCC supply current, volatile write/read fSCL = 400kHz;SDA = Open; (for I 2C, Active, Read and Volatile Write States only) 200 µA IV-1 V- supply current, volatile write/read fSCL = 400kHz;SDA = Open; (for I 2C, Active, Read and Volatile Write States only) -100 µA ICC2 VCC supply current, non volatile write fSCL = 400kHz; SDA = Open; (for I 2C, Active, Nonvolatile Write State only) 200 µA IV-2 V- supply current, nonvolatile write fSCL = 400kHz; SDA = Open; (for I 2C, Active, Nonvolatile Write State only) -3 mA ICCSB VCC current (standby) VCC = +5.5V, I 2C Interface in Standby State 1 µA VCC = +3.6V, I 2C Interface in Standby State 1 µA IV-SB V- current (standby) V- = -5.5V, I2C Interface in Standby State -5 µA V- = -3.6V, I2C Interface in Standby State -2 µA ILkgDig Leakage current, at pins SDA, SCL, A0, and A1 Voltage at pin from GND to VCC -10 10 µA tDCP (Note 13) DCP wiper response time SCL falling edge of last bit of DCP Data Byte to wiper change 1µs Vpor Power-on recall for both V- and VCC V- -2.5 V VCC 2.5 V V-Ramp V- ramp rate 0.2 V/ms tD (Note 13) Power-up delay VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state 3ms EEPROM SPECS EEPROM Endurance 200,000 Cycles EEPROM Retention Temperature ≤ +75°C 50 Years SERIAL INTERFACE SPECS VIL A0, A1, SDA, and SCL input buffer LOW voltage -0.3 0.3*VCC V VIH A0, A1, SDA, and SCL input buffer HIGH voltage 0.7*VCC VCC+ 0.3 V Hysteresis SDA and SCL input buffer hysteresis 0.05* VCC V VOL SDA output buffer LOW voltage, sinking 4mA 00.4 V Cpin (Note 15) A0, A1, SDA, and SCL pin capacitance 10 pF fSCL SCL frequency 400 kHz tIN Pulse width suppression time at SDA and SCL inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL falling edge to SDA output data valid SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window. 900 ns tBUF Time the bus must be free before the start of a new transmission SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. 1300 ns tLOW Clock LOW time Measured at the 30% of VCC crossing. 1300 ns tHIGH Clock HIGH time Measured at the 70% of VCC crossing. 600 ns tSU:STA START condition setup time SCL rising edge to SDA falling edge. Both crossing 70% of VCC. 600 ns ISL95711 |
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