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ISL6219ACA Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6219ACA Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 17 page 9 FN9093.1 March 20, 2007 In some circumstances, it may be necessary to deliberately design some channel-current unbalance into the system. In a highly compact design, one or two channels may be able to cool more effectively than the other(s) due to nearby air flow or heat sinking components. The other channel(s) may have more difficulty cooling with comparatively less air flow and heat sinking. The hotter channels may also be located close to other heat-generating components tending to drive their temperature even higher. In these cases, a proper selection of the current sense resistors (RISEN in Figure 4) introduces channel current unbalance into the system. Increasing the value of RISEN in the cooler channels and decreasing it in the hotter channels moves all channels into thermal balance at the expense of current balance. OVERCURRENT PROTECTION The average current, IAVG in Figure 5, is continually compared with a constant 75 μA reference current. If the average current at any time exceeds the reference current, the comparator triggers the converter to shut down. All PWM signals are placed in a high-impedance state which signals the drivers to turn off both upper and lower MOSFETs. The system remains in this state while the controller counts 2048 phase-clock cycles. This is followed by a soft-start attempt (see Soft-Start). If the soft-start attempt is successful, operation will continue as normal. Should the soft-start attempt fail, the ISL6219A repeats the 2048-cycle wait period and follows with another soft-start attempt. This hiccup mode of operation continues indefinitely as shown in Figure 6 as long as the controller is enabled or until the overcurrent condition resolves. VOLTAGE REGULATION The ISL6219A uses a digital to analog converter (DAC) to generate a reference voltage based on the logic signals at pins VID4 to VID0. The DAC decodes the a 5-bit logic signal (VID) into one of the discrete voltages shown in Table 1. Each VID input offers a 20mA pull up to 2.5V for use with open- drain outputs. External pull-up resistors or active-high output- stages can augment the pull-up current sources, but a slight accuracy error can occur if they are pulled above 2.9V. The integrating compensation network shown in Figure 7 assures that the steady-state error in the output voltage is limited to the error in the reference voltage (output of the DAC) plus offset errors in the error amplifier. Intersil specifies the guaranteed tolerance of the ISL6219A to include all variations in the amplifiers and reference so that the output voltage remains within the specified system tolerance. FIGURE 5. CHANNEL-1 PWM FUNCTION AND CURRENT- BALANCE ADJUSTMENT ÷ N IAVG I3 I2 Σ - + + - + - f(j ω) PWM1 I1 VCOMP SAWTOOTH SIGNAL IER 0A 0V 5ms/DIV OUTPUT VOLTAGE, OUTPUT CURRENT, 20A/DIV FIGURE 6. OVERCURRENT BEHAVIOR IN HICCUP MODE 500mV/DIV FIGURE 7. OUTPUT-VOLTAGE AND LOAD-LINE REGULATION - + IAVG REFERENCE EXTERNAL CIRCUIT ISL6219A INTERNAL CIRCUIT COMP CC RC RFB FB VSEN - + VDROOP ERROR AMPLIFIER VOUT VOLTAGE(VDAC) VCOMP ISL6219A |
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