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ISL6612EIB Datasheet(PDF) 7 Page - Intersil Corporation

Part # ISL6612EIB
Description  Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6612EIB Datasheet(HTML) 7 Page - Intersil Corporation

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7
FN9153.8
February 26, 2007
Description
Operation
Designed for versatility and speed, the ISL6612 and ISL6613
MOSFET drivers control both high-side and low-side
N-Channel FETs of a half-bridge power train from one
externally provided PWM signal.
Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated; the upper gate
(UGATE) is held low and the lower gate (LGATE), controlled by
the Pre-POR overvoltage protection circuits, is connected to the
PHASE. Once the VCC voltage surpasses the VCC Rising
Threshold (see “Electrical Specifications” on page 5), the PWM
signal takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [tPDLL], the lower
gate begins to fall. Typical fall times [tFL] are provided in
“Electrical Specifications” on page 5. Adaptive shoot-through
circuitry monitors the PHASE voltage and determines the upper
gate delay time [tPDHU]. This prevents both the lower and
upper MOSFETs from conducting simultaneously. Once this
delay period is complete, the upper gate drive begins to rise
[tRU] and the upper MOSFET turns on.
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [tPDLU] is encountered before the upper
gate begins to fall [tFU]. Again, the adaptive shoot-through
circuitry determines the lower gate delay time, tPDHL. The
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See the following
section for details). The lower gate then rises [tRL], turning on
the lower MOSFET.
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
These drivers incorporate a unique adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFETs’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other
has turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.2V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the rDS(ON)
drop in the phase voltage preventing from false detection of the
-0.2V phase level during rDS(ON conduction period. In the case
of zero current, the UGATE is released after 35ns delay of the
LGATE dropping below 0.5V. During the phase detection, the
disturbance of LGATE’s falling transition on the PHASE node is
blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
Three-State PWM Input
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds (outlined in “Electrical Specifications” on page 5)
determine when the lower and upper gates are enabled.
PWM
UGATE
LGATE
tFL
tPDHU
tPDLL
tRL
tTSSHD
tPDTS
tPDTS
1.5V<PWM<3.2V
1.0V<PWM<2.6V
tFU
tRU
tPDLU
tPDHL
tTSSHD
FIGURE 1. TIMING DIAGRAM
ISL6612, ISL6613


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