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ISL6548CRZA Datasheet(PDF) 1 Page - Intersil Corporation |
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ISL6548CRZA Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 15 page 1 ® CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6548 ACPI Regulator/Controller for Dual Channel DDR Memory Systems The ISL6548 provides a complete ACPI compliant power solution for up to 4 DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply VDDQ during S0/S1 and S3 states. During S0/S1 state, a fully integrated sink-source regulator generates an accurate (VDDQ/2) high current VTT voltage without the need for a negative supply. Two LDO controllers are also integrated for the GMCH core voltage regulation and for the GMCH/CPU VTT termination voltage regulation. The switching PWM controller drives two N-Channel MOSFETs in a synchronous-rectified buck converter topology. The synchronous buck converter uses voltage- mode control with fast transient response. The switching regulator provides a maximum static regulation tolerance of ± 2% over line, load, and temperature ranges. The output is user-adjustable by means of external resistors down to 0.8V. An integrated soft-start feature brings all outputs into regulation in a controlled manner when returning to S0/S1 state from any sleep state. During S0 the VIDPGD signal indicates that the GMCH/CPU VTT termination voltage is within spec and operational. Each output is monitored for undervoltage events. The switching regulator also has overvoltage and overcurrent protection. Thermal shutdown is integrated. Pinout ISL6548 (6x6 QFN) TOP VIEW Features • Generates 4 Regulated Voltages - Synchronous Buck PWM Controller for DDR VDDQ - 3A Integrated Sink/Source Linear Regulator with Accurate VDDQ/2 Divider Reference for DDR VTT - LDO Regulator for GMCH Core - Sink/Source LDO Regulator for CPU/GMCH VTT Termination • ACPI Compliant Sleep State Control • Glitch-free Transitions During State Changes • PWM Controller Drives Low Cost N-Channel MOSFETs • 250kHz Constant Frequency Operation • Tight Output Voltage Regulation - All Outputs: ±2% Over Temperature • Fully-Adjustable Outputs with Wide Voltage Range: Down to 0.8V supports DDR and DDR2 Specifications • Simple Single-Loop Voltage-Mode PWM Control Design • Fast PWM Converter Transient Response • Under and Overvoltage Monitoring on All Outputs • OCP on the Switching Regulator • Integrated Thermal Shutdown Protection • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Single and Dual Channel DDR Memory Power Systems in ACPI compliant PCs • Graphics Cards - GPU and Memory Supplies • ASIC Power Supplies • Embedded Processor and I/O Supplies • DSP Supplies 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 DRIVE4 REFADJ4 DRIVE3 FB3 FB4 COMP FB 5VSBY S3# P12V GND DDR_VTT DDR_VTT VDDQ GND 29 Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL6548CRZA (Note) ISL6548CRZ 0 to 70 28 Ld 6x6 QFN (Pb-free) L28.6x6 ISL6548CRZA-T (Note) ISL6548CRZ 0 to 70 28 Ld 6x6 QFN Tape and Reel (Pb-free) L28.6x6 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet FN9188.2 January 3, 2006 |
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