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BQ4010Y Datasheet(PDF) 11 Page - Texas Instruments |
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BQ4010Y Datasheet(HTML) 11 Page - Texas Instruments |
11 / 18 page www.ti.com Address Data−In Valid High−Z DOUT Data Undefined (1) tWZ tOW tDW tDH1 tWP tAS tCW tAW tWR1 tWC DIN WE CE bq4010/Y/LY SLUS116A – MAY 1999 – REVISED APRIL 2007 Table 3. WRITE CYCLE (TA = TOPR, VCC(min)≤ VCC≤ VCC(max)) -70 -85 -150 -200 PARAMETER TEST CONDITIONS UNIT MIN MAX MIN MAX MIN MAX MIN MAX tWC Write cycle time 70 85 150 200 tCW Chip enable to end of write See (1) 65 75 100 150 tAW Address valid to end of write See (1) 65 75 90 150 Measured from address valid to tAS Address setup time 0 0 0 0 beginning of write.(2) Measured from beginning of write to tWP Write pulse width 55 65 90 130 end of write. (1) Measured from WE going high to end tWR1 Write recovery time (write cycle 1) 5 5 5 5 of write cycle.(3) ns Measured from CE going high to end tWR2 Write recovery time (write cycle 2) 15 15 15 15 of write cycle.(3) Measured to first low-to- high transition tDW Data valid to end of write 30 35 50 70 of either CE or WE. Measured from WE going high to end tDH1 Data hold time (write cycle 1) 0 0 0 0 of write cycle.(4) Measured from CE going high to end tDH2 Data hold time (write cycle 2) 0 0 0 0 of write cycle.(4) tWZ Write enbled to output in high Z I/O pins are in output state.(5) 0 25 0 30 0 50 0 70 tOW Output active from end of write 5 5 5 5 I/O pins are in output state. (5) (1) A write ends at the earlier transition of CE going high and WE going high. (2) A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low. (3) Either tWR1 or tWR2 must be met. (4) Either tDH1 or tDH2 must be met. (5) If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state. (1) CE or WE must be high during address transition. (2) Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. (3) If OE is high, the I/O pins remain in a state of high impedance. Figure 8. Write Cycle No. 1 (WE-Controlled) (1)(2)(3) 11 Submit Documentation Feedback |
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